Intel Unveils 10nm SuperFin, Willow Cove, Tiger Lake, Xe Graphics, Ice Lake, Sapphire Rapids, Alder Lake and Hybrid Bonding Technologies

Intel announced at its 2020 Architecture Day that the new 10nm SuperFin transistor technology will deliver the company’s most powerful single‑node performance boost to date.

The 10nm SuperFin process will be used in the next‑generation mobile processor codenamed “Tiger Lake,” which is already in production and expected to reach OEM products during the holiday season.

In addition, Intel unveiled the Willow Cove CPU micro‑architecture, the Tiger Lake SoC architecture, and the fully‑scalable Xe graphics architecture, all of which will be applied to consumer, high‑performance computing, mobile client, and gaming markets.

Intel’s chief architect Raja Koduri and several senior architects presented updates across six technology pillars: process/packaging, architecture, memory/storage, interconnect, security, and software.

01

10nm SuperFin Technology: Comparable to Full‑Node Transition

SuperFin combines enhanced FinFET transistors with Super MIM capacitors, providing improved source/drain epitaxy, refined gate processes, and additional gate spacing.

Intel claims the performance gain rivals a full‑node transition.

SuperFin achieves performance improvements through five transistor‑level optimizations:

1. Optimized source/drain structure – Extended epitaxial growth reduces resistance and increases current flow.

2. Improved gate process – Enhances channel mobility for faster charge carrier movement.

3. Additional gate spacing – Provides higher drive current for peak‑performance chip functions.

4. New thin‑wall – Lowers via resistance by 30% and boosts interconnect performance.

5. Increased capacitance – Offers five‑times the capacitance per unit area, reducing voltage drop and raising performance.

The technology uses a high‑K dielectric stacked in ultra‑thin layers to form a super‑lattice structure.

02

Willow Cove and Tiger Lake CPU Architectures

Built on the 10nm SuperFin process, Intel introduced the Willow Cove micro‑architecture, which improves performance, frequency, and power efficiency over the 2018 Sunny Cove design.

Willow Cove adds a redesigned 1.25 MB MLC cache and incorporates Control Flow Enforcement Technology for enhanced security.

Tiger Lake is Intel’s first SoC to use the new low‑power Xe‑LP graphics architecture, optimizing CPU, AI accelerator, and graphics performance.

The Tiger Lake SoC features eight key innovations:

1. New Willow Cove CPU cores – SuperFin‑based cores with higher frequencies.

2. New Xe graphics – Up to 96 execution units, greatly improving performance‑per‑watt.

3. Power management – Integrated DVFS and FIVR for better voltage regulation.

4. Architecture and memory – Bandwidth doubled to ~86 GB/s, supporting LP4x‑4267, DDR4‑3200, and LP5‑5400.

5. GNA 2.0 AI accelerator – Low‑power neural inference reduces CPU load by 20 % during audio noise‑suppression workloads.

6. I/O – Integrated Thunderbolt 4/USB4 and PCIe Gen 4 for low‑latency, high‑bandwidth device access.

7. Display – Up to 64 GB/s synchronous bandwidth supporting multiple high‑resolution displays.

8. IPU6 – Six sensors delivering up to 4K 30 fps video and 27 MP stills, with 4K 90 fps video capability.

03

Xe Graphics Family and Discrete GPUs

Intel detailed its fully‑scalable Xe graphics architecture, which includes four series: Xe‑LP, Xe‑HP, Xe‑HPC, and Xe‑HPG.

1. Xe‑LP – Optimized for PCs and mobile platforms, offering up to 96 EU units, asynchronous compute, view instancing, sampler feedback, AV1‑enabled media engine, and an updated display engine.

Xe‑LP supports instant game tuning, capture/streaming, and image sharpening, with driver improvements via a new DX11 path and optimized compiler.

2. Xe‑HP – Multi‑tiled, highly scalable high‑performance architecture for data‑center and rack‑level media workloads, providing GPU scalability and AI acceleration.

Demonstrations showed Xe‑HP transcoding ten 4K video streams at 60 fps on a single tile and scaling across multiple tiles.

Intel’s first Xe‑HP chip has completed lab testing and is being validated with key customers, with broader availability planned for next year.

3. Xe‑HPG – Gaming‑focused variant that combines Xe‑LP efficiency with Xe‑HP scalability and Xe‑HPC performance, adding a GDDR6‑based memory subsystem and hardware‑accelerated ray tracing, slated for 2021 shipment.

Intel will launch two discrete GPUs based on Xe architecture: the DG1 (Xe‑LP) for PCs, now in early‑access via Intel DevCloud, and the SG1 (Server GPU) for data‑center workloads, integrating four DG1 dies for low‑latency, high‑density cloud gaming and video streaming.

04

Data‑Center Architectures: Ice Lake and Sapphire Rapids

Ice Lake – Intel’s first 10nm Xeon Scalable processor, delivering strong throughput and latency across diverse workloads, featuring full‑memory encryption, PCIe Gen 4, eight memory channels, and enhanced instruction sets for faster cryptographic operations. Expected launch by year‑end.

Sapphire Rapids – Next‑gen Xeon Scalable built on enhanced SuperFin, supporting DDR5, PCIe Gen 5, Compute Express Link 1.1, and the AMX matrix‑extension accelerator. Chosen for the Aurora exascale system at Argonne National Lab, with first shipments slated for H2 2021.

Intel also highlighted advances in FPGA technology, including the world’s first 224 G‑PAM4 TX/RX transceiver.

05

Next‑Generation Hybrid Architecture: Alder Lake

Intel’s upcoming client product Alder Lake will combine the newly announced Golden Cove and Gracemont cores in a hybrid design to improve performance‑per‑watt.

06

Hybrid Bonding Packaging: Test Chip Shipped

Hybrid bonding, an alternative to traditional thermocompression bonding, enables sub‑10 µm pitch, delivering higher interconnect density, bandwidth, and lower power.

Intel’s test chip using hybrid bonding has successfully completed tape‑out in Q2 of this year.

07

Software: oneAPI Gold Release Planned for This Year

Intel released oneAPI Beta 8 in July, adding new capabilities for distributed data analysis, rendering performance, profiling, video, and threading libraries.

The upcoming oneAPI Gold version, slated for later this year, will provide developers with a production‑grade solution across scalar, vector, matrix, and spatial architectures.

08

Conclusion: Intel’s Losses and Gains

Recent setbacks such as the delayed 7nm CPU launch and Nvidia surpassing Intel’s market cap have raised industry concerns.

Nevertheless, Intel’s Architecture Day demonstrates continued technical strength and confidence, expanding beyond Moore’s Law by innovating across CPUs, GPUs, FPGAs, architecture, packaging, and software to meet diverse computing demands.

The company’s six‑pillar strategy—covering process/packaging, architecture, memory/storage, interconnect, security, and software—offers a comprehensive solution for industry advancement.

Whether Intel can maintain its leadership amid intensifying competition remains to be seen.

Source: 芯东西