No ARM, No x86! How RISC‑V + Open‑Source HarmonyOS Empower Software Engineers to Build Their Own Chip

Amid the 2026 AI‑coding boom, traditional software firms face an "anxiety period" as AI agents could replace many employees; Red Elephant Cloud (红象云腾) therefore re‑examined its business model and, drawing on its big‑data background, decided to explore chip design.

Founder Tong Xiaojun, who previously built search engines serving hundreds of millions of users and a Hadoop platform supporting Chinese remote‑sensing satellites and domestic CPUs such as Feiteng, Loongson and OpenPower, spent the second half of 2025 with two colleagues designing an AI‑accelerator chip. Using AI‑coding tools for RTL drafting, they created the "Pi Dan 1" chip on the open‑source RISC‑V ISA, adopting Microsoft’s BitNet ternary‑quantization (weights –1, 0, 1 represented with 1.58 bits, 8‑bit activations) and fabricating it on a 55 nm open‑source PDK. By June 2026 the chip was cut, packaged, and awaiting power‑efficiency validation.

The project relied on China’s “One‑Chip‑Per‑Life” talent program and the OpenECOS open‑source EDA/PDK initiative, which provide shared tape‑out slots (“拼片”) that split mask costs among teams, reducing a 55 nm run from nearly one million yuan to a manageable amount. OpenECOS and Zhejiang Chuangxin’s 55 nm PDK have reached prototype‑verification readiness, though mass‑production still depends on commercial EDA tools.

RISC‑V’s open, royalty‑free architecture contrasts with ARM’s multi‑million‑yuan licensing fees and x86’s closed nature; forecasts predict 800 billion RISC‑V chips shipped in 2025, making it a de‑facto standard for new designs.

Open‑source HarmonyOS combined with RISC‑V offers a low‑power embedded OS, creating a compelling hardware‑software stack for edge devices. BitNet’s ternary quantization theoretically yields >1000× compute‑unit speedup, but memory bandwidth remains a bottleneck; empirical tests show <10 % accuracy loss on dialogue and search benchmarks, acceptable for many edge scenarios.

Practical use cases highlighted include ultra‑low‑power wake‑word detection, video semantic compression, and other edge AI tasks where "Pi Dan 1" can listen continuously with minimal power and switch to higher performance when needed.

Tong emphasizes that chip design is largely software: RTL coding accounts for ~30 % of effort, while verification and sign‑off consume >70 %. Software engineers can handle front‑end logic design, but back‑end physical design, timing closure and sign‑off remain challenging.

Future goals involve building FPGA‑cluster simulators for large open‑source chips (e.g., "Xiangshan Processor‑Kunming Lake V3") and integrating BitNet modules into data‑center‑class AI accelerators, leveraging the company’s long‑standing data‑center expertise.

In summary, the convergence of open‑source RISC‑V, HarmonyOS, open EDA/PDK, and AI‑assisted design lowers three major barriers—ISA licensing, design‑tool cost, and verification access—enabling software engineers to prototype chips, though moving from prototype to volume production still requires overcoming significant back‑end and yield challenges.