SpaceX is planning a multibillion‑dollar effort to design and manufacture a custom AI GPU that can survive the extreme temperature, radiation, and power constraints of space while also serving Tesla’s edge‑computing needs, confronting severe technical, ecosystem, and capital challenges.
Arm has shifted from pure IP licensing to launching its own Neoverse processor, securing Meta as the first customer, a move that could reshape semiconductor power dynamics by compressing the value chain and intensifying competition among chip designers and server manufacturers.
This article provides a comprehensive, step‑by‑step overview of digital chip design, covering specification definition, system architecture, front‑end logic design, back‑end physical implementation, verification, sign‑off, and tape‑out, complete with diagrams and practical insights into each stage.
Huawei is developing a new AI‑focused GPU‑style chip that mirrors Nvidia and AMD architectures, aiming to ease Chinese developers’ shift from Nvidia hardware, but still faces software compatibility hurdles due to reliance on CUDA and ongoing U.S. export restrictions.
This article explains what ASIC chips are, how they differ from CPUs, GPUs and FPGAs, classifies them by customization level and function, outlines their performance and cost advantages, discusses their drawbacks, and reviews current products and market trends driving AI hardware adoption.
US CTO David Sachs warned that China’s AI and semiconductor capabilities are merely one to two years behind the United States, highlighting Huawei’s rapid progress in GPU design, the potential impact of export controls, and the broader implications for global tech competition.
Broadcom’s market‑cap breakthrough past $1 trillion highlights its strategic push into AI ASICs, revealing how ASIC‑FPGA trade‑offs, collaborations with Google, and competition with Nvidia’s GPU ecosystem are reshaping the high‑performance computing landscape.
This article provides a comprehensive overview of Ethernet switches, covering their definitions, multiple classification dimensions, architectural roles in campus, enterprise, and data‑center scenarios, component makeup, market dynamics between black‑box and white‑box solutions, and future trends in switch chip development.
In just two weeks, engineer Adam Majmudar designed and implemented a minimalist GPU called tiny‑gpu—complete with a custom 11‑instruction ISA, Verilog RTL, and verified via OpenLane—sharing the open‑source project on GitHub, earning thousands of stars, and preparing it for fabrication through Tiny Tapeout 7, showcasing how modern tools make DIY chip design increasingly accessible.
This article provides a comprehensive overview of ASIC chips, covering their definition, material composition, classification by customization level and application, key advantages and drawbacks, notable product examples, and emerging market opportunities across AI, edge computing, and consumer electronics.
AMD’s new Versal Premium VP1902 FPGA, the world’s largest adaptive SoC, doubles logic capacity over its predecessor, adds extensive high‑speed transceivers, NoC and PCIe upgrades, and promises faster debugging and AI‑driven chip validation, marking a significant shift in semiconductor prototyping.
Chinese researchers used generative AI to design Qǐ Méng 1, the first completely self‑generated CPU chip that runs Linux and rivals early Intel 486 performance, showcasing the rapid rise of AI‑driven semiconductor design.
The U.S. added cutting‑edge electronic design automation (EDA) software and related semiconductor technologies to its export control list, prompting concerns about short‑term disruptions and long‑term constraints on China's advanced chip design while also spurring domestic EDA development.
This article provides a detailed, line‑by‑line analysis of a chart comparing FPGA and ASIC across dimensions such as upfront costs, unit cost, time‑to‑market, performance, power consumption, field updates, density, design flow, granularity, verification needs, upgrade paths, and additional features, helping engineers decide which technology best fits their high‑performance AI workloads.
The article presents a detailed technical review of Kunlun Chip's XPU‑R AI accelerator, covering its evolution from early FPGA prototypes to the current 7nm, 256 TOPS chip, the architectural choices that address AI workload demands, performance advantages over CPUs/GPUs, and the product ecosystem supporting diverse AI scenarios.
The 2022 Beijing Zhiyuan Conference report by Kunlun Core’s chip R&D director outlines AI chip market opportunities and challenges, describes the company’s shift from FPGA clusters to a programmable XPU‑R architecture with 7nm, 256 TOPS INT8 performance, GDDR6 memory and PCIe 4.0, and details current deployments and plans for third‑ and fourth‑generation chips.
Tencent’s hardware teams evolved from a lack of verification tools in 2019 to building AI inference chips, video‑encoding silicon, and intelligent NICs, overcoming FPGA challenges, scaling cloud infrastructure, and delivering high‑performance, low‑cost solutions for massive multimedia and AI workloads.
Chinese domestic GPU development has accelerated rapidly, driven by fast‑track product launches, strategic IP licensing from firms like Imagination Technologies, and supportive policies, while industry players navigate challenges of patents, design complexity, and market competition to bring full‑function GPUs to market.
The article traces Apple’s four‑decade struggle with thermal challenges in its Mac lineup, recounting the legacy of the 2013 “trash‑can” Mac Pro, the evolution of chip architecture, and how the company’s shift to self‑designed silicon like the M1 series finally broke the heat‑constraint cycle.
The article explains how RISC‑V’s open, customizable ISA, the shift toward free and unrestricted hardware design, and market pressures such as Moore’s law slowdown and AI‑driven compute demand together fuel its rapid adoption, ecosystem growth, and competitive edge over proprietary architectures.
This article outlines the methodology, key decision factors, and practical scenarios for moving electronic design automation (EDA) environments to the cloud, comparing hybrid and full‑cloud solutions for large design firms and start‑ups, and presents case studies such as STA migration.
This article provides a comprehensive overview of ASIC chips, covering their definition, hardware composition, classification by customization and function, key advantages and drawbacks, notable product examples, and emerging market trends driving growth across AI, security, and consumer electronics.
Amid global chip shortages and shifting market dynamics, Chinese internet powerhouses like ByteDance, Tencent, and Xiaomi, alongside global players such as Google, Intel, and Nvidia, are accelerating their own semiconductor initiatives, reshaping the industry from smartphone SoCs to AI‑focused cloud processors.
The article explains how artificial intelligence relies on algorithms, compute and data, compares engineering and simulation methods, and details the roles, architectures, performance and energy characteristics of GPUs, FPGAs, and ASICs as the primary hardware accelerators for modern deep‑learning applications.
The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.
The article analyzes RISC‑V’s open, modular ISA, its technical advantages over legacy architectures, the rapidly maturing global and Chinese ecosystems, real‑world applications, and strategic recommendations for China to build an independent, competitive semiconductor industry amid trade tensions and policy drives.
The article provides a comprehensive overview of RISC‑V, covering its origins amid trade‑war pressures, open‑source technical characteristics, growing global and Chinese ecosystem, comparisons with ARM and x86, and its emerging role in low‑power, customizable chips for IoT and AI applications.
The article provides a comprehensive overview of the open‑source RISC‑V instruction set, its historical development, technical benefits such as modularity and a minimal instruction set, and its growing relevance across IoT, mobile, server, storage, AI, and security domains, while also discussing ecosystem challenges and industry initiatives.
This article offers a comprehensive overview of Huawei's three‑decade chip development, detailing the evolution of its AI, computing, mobile SoC, 5G communication, IoT, and video chips, their technical specifications, market impact, and future roadmap within China's semiconductor landscape.
This article traces Huawei’s three‑decade journey from its modest 1991 chip beginnings to a diversified portfolio of five major series—Kirin, Kunpeng, Ascend, Balong/Tiangang, Boudica/Lingxiao, and Honghu—detailing their technical evolution, market impact, and future roadmap across mobile, compute, AI, 5G, IoT, and video domains.
Five 2016‑class undergraduates from the University of Chinese Academy of Sciences completed a 64‑bit RISC‑V SoC chip named "NutShell," successfully fabricated it in 110 nm, ran Linux and a custom teaching OS, and presented the open‑source design at the RISC‑V Global Forum, showcasing a novel "One Life One Chip" education model.
Alibaba's DAMO Academy outlines ten disruptive technology trends for 2020—including AI’s shift to cognitive intelligence, compute‑storage integration, industrial‑Internet hyper‑convergence, massive machine collaboration, modular chip design, mass‑scale blockchain, quantum computing breakthroughs, new semiconductor materials, privacy‑preserving AI, and cloud‑centric innovation—offering a comprehensive outlook on the next wave of digital transformation.
The 2020 DAMO Academy report outlines ten transformative technology trends—including the shift from perceptual to cognitive AI, compute‑storage integration, industrial‑internet hyper‑convergence, large‑scale multi‑agent collaboration, modular chip design, mass‑market blockchain, quantum‑computing breakthroughs, new semiconductor materials, privacy‑preserving AI, and cloud as the core of IT innovation—highlighting their potential impact on the next decade of tech development.
The article provides a detailed, English-language overview of the entire integrated circuit design flow—from architecture and algorithm selection through RTL coding, verification, synthesis, layout, and sign‑off—highlighting the roles, tools, and challenges faced by engineers in modern ASIC and FPGA development.
