Tagged articles

RISC-V

62 articles · Page 1 of 1

ByteDance SYS Tech

Oct 18, 2026 · Backend Development

ByteDance 2026 Linux Kernel Review: 198 Commits, Preemptible IPI, Dying Memcg Fixes

ByteDance's STE team details 198 accepted Linux kernel commits in 2026 H1, including making IPI waits preemptible to cut tail latency by 90%, solving dying memory cgroups with 33 patches, restructuring HugeTLB vmemmap optimization, accelerating large memory device initialization, and adding iomap fast paths for small direct I/O, plus extensive community review participation.

Linux kernelRISC-Vfilesystems

0 likes · 29 min read

ByteDance 2026 Linux Kernel Review: 198 Commits, Preemptible IPI, Dying Memcg Fixes

Architects' Tech Alliance

Sep 1, 2026 · Industry Insights

$1.4 Trillion Valuation: China’s Unicorn List Highlights Beijing’s Four Semiconductor Leaders

The GEI China Unicorn Enterprise Research Report 2026 shows that China’s unicorns reached a total valuation of over $1.4 trillion in 2025, with more than 80 % in hard‑tech fields and Beijing’s four semiconductor unicorns—Qingwei Intelligent, Kunlun Chip, SMIC Beijing and Yiswei Computing—accounting for over 1300 billion RMB and leading the industry’s shift from internet to advanced chip technologies.

AIChinaRISC-V

0 likes · 4 min read

$1.4 Trillion Valuation: China’s Unicorn List Highlights Beijing’s Four Semiconductor Leaders

Aug 29, 2026 · Operations

Ubuntu 26.04.1 Released – How 24.04 Users Can Upgrade Early with a Single Command

Ubuntu 26.04.1 LTS point release bundles four months of security patches and bug fixes, introduces no new features or kernel, and offers a single manual upgrade path for 24.04 users via the do-release-upgrade -d command, while other users can simply update in place.

LTSRISC-VSDXL

0 likes · 11 min read

Ubuntu 26.04.1 Released – How 24.04 Users Can Upgrade Early with a Single Command

IT Learning Made Simple

Aug 17, 2026 · Fundamentals

CISC vs RISC: How Complex and Simple Instruction Sets Compete

This article explains the fundamental differences between CISC and RISC architectures, covering their historical origins, design philosophies, characteristic trade‑offs, representative implementations, modern hybrid approaches, and the rising impact of ARM and RISC‑V in today’s computing landscape.

ARMCISCCPU architecture

0 likes · 9 min read

CISC vs RISC: How Complex and Simple Instruction Sets Compete

Linux Kernel Journey

Jul 21, 2026 · Industry Insights

Partitioning Is Mandatory: The Cost of Heterogeneous RISC‑V and Single‑Kernel Designs

The Key Stone K3’s 16‑core RISC‑V SoC, half of which are 1024‑bit vector AI cores, forces Linux to reject mismatched cores, revealing that economic constraints make core partitioning unavoidable and that a multi‑kernel approach is the only viable solution.

CPU partitioningLinux kernelRISC-V

0 likes · 19 min read

Partitioning Is Mandatory: The Cost of Heterogeneous RISC‑V and Single‑Kernel Designs

Jun 18, 2026 · Industry Insights

No ARM, No x86! How RISC‑V + Open‑Source HarmonyOS Empower Software Engineers to Build Their Own Chip

The article recounts how a big‑data software veteran leveraged AI‑assisted coding, the open‑source RISC‑V ISA, BitNet ternary quantization and open‑source EDA/PDK to design and tape‑out the "Pi Dan 1" AI accelerator, illustrating the technical, cost and ecosystem factors that make chip prototyping feasible for software engineers.

AI acceleratorBitNetHarmonyOS

0 likes · 14 min read

No ARM, No x86! How RISC‑V + Open‑Source HarmonyOS Empower Software Engineers to Build Their Own Chip

Architects' Tech Alliance

May 21, 2026 · Industry Insights

DPU Deep Dive: The Hidden Workhorse Powering Data Centers

The article provides a comprehensive analysis of Data Processing Units (DPUs), detailing their role as off‑load engines in data centers, the rapid global market growth with China leading the surge, key technology trends, competitive landscape, and the major challenges that must be overcome for broader adoption.

AIChipletDPU

0 likes · 12 min read

DPU Deep Dive: The Hidden Workhorse Powering Data Centers

IoT Full-Stack Technology

Apr 21, 2026 · Industry Insights

ESP32‑S31 Debuts with Dual‑Core RISC‑V, 62 GPIO and Gigabit Ethernet

Espressif's upcoming ESP32‑S31 is a dual‑core RISC‑V wireless MCU featuring a high‑performance core with FPU/SIMD, a low‑power core, 62 GPIO, gigabit Ethernet, Wi‑Fi, Bluetooth, 802.15.4, plus a rich set of peripherals, while offering fewer multimedia interfaces than the ESP32‑P4.

ESP32-S31RISC-VSOC

0 likes · 4 min read

ESP32‑S31 Debuts with Dual‑Core RISC‑V, 62 GPIO and Gigabit Ethernet

IoT Full-Stack Technology

Apr 21, 2026 · Industry Insights

What’s New in the Upcoming ESP32‑S31 Compared to the ESP32‑P4?

The ESP32‑S31 is a new dual‑core RISC‑V wireless microcontroller from Espressif featuring a high‑performance core, low‑power core, 62 GPIO, gigabit Ethernet, Wi‑Fi, Bluetooth, 802.15.4, GPU, VPU and extensive peripherals, but it lacks some multimedia interfaces found in the ESP32‑P4, making its media capabilities more limited while still being possibly the most powerful ESP32 SoC released.

ESP32-S31EspressifRISC-V

0 likes · 3 min read

What’s New in the Upcoming ESP32‑S31 Compared to the ESP32‑P4?

Radish, Keep Going!

Nov 12, 2025 · Fundamentals

From Erlang to FFmpeg: 10 Must-Read Tech Stories Shaping Modern Development

This roundup highlights ten compelling tech stories—from falling in love with Erlang's fault‑tolerant concurrency and uncovering a historic Unix v4 tape, to warnings about "vibe coding" on RISC‑V, lazygit's Git UI boost, privacy concerns over Flock Safety cameras, Buffett's final shareholder letter, the legacy of Toy Story, SoftBank's Nvidia exit, Apple's iPhone Pocket, and FFmpeg's plea for funding—offering insights for developers and enthusiasts alike.

FFmpegGitRISC-V

0 likes · 9 min read

From Erlang to FFmpeg: 10 Must-Read Tech Stories Shaping Modern Development

Linux Kernel Journey

Nov 7, 2025 · Industry Insights

Celebrating 20 Years of Linux Kernel Innovation: Highlights from the 20th CLK Conference

The 20th China Linux Kernel (CLK) Conference in Shenzhen gathered nearly 500 developers on‑site and over 170,000 online viewers, showcasing five technical sub‑forums, keynote insights on AI‑driven kernel challenges, RISC‑V adoption, and a 31‑fold rise in Chinese kernel contributors, underscoring the rapid evolution of China’s kernel ecosystem.

AIChinaLinux kernel

0 likes · 13 min read

Celebrating 20 Years of Linux Kernel Innovation: Highlights from the 20th CLK Conference

Aug 28, 2025 · Fundamentals

What’s New in LLVM 21.1.0? A Deep Dive into the Latest Compiler Features

LLVM 21.1.0, released on August 26, introduces the AMD GFX1250 target, enhancements to the AMDGPU backend, support for NVIDIA GB10 CPUs, RISC‑V improvements, and LLDB debugger upgrades, and is freely available for download from the official GitHub releases page.

AMD GFX1250LLDBLLVM

0 likes · 2 min read

What’s New in LLVM 21.1.0? A Deep Dive into the Latest Compiler Features

Java Tech Enthusiast

Aug 24, 2025 · Backend Development

Why Linus Torvalds Called Recent RISC‑V Patches ‘Garbage’ and What It Means for Linux 6.17

Linus Torvalds sharply rejected a late RISC‑V patch set submitted to Linux 6.17, labeling it garbage and warning developers to avoid low‑quality, last‑minute contributions, while the community debates the technical changes and the broader implications for kernel development.

Linus TorvaldsLinuxRISC-V

0 likes · 7 min read

Why Linus Torvalds Called Recent RISC‑V Patches ‘Garbage’ and What It Means for Linux 6.17

Aug 16, 2025 · Fundamentals

Why bcachefs Was Dropped from Linux 6.17 – Linus’s Fury and COW Outlook

Linux kernel 6.17’s first release candidate arrived without any bcachefs changes, as Linus Torvalds expressed anger over delayed RISC‑V patches, while developers debate the future of the advanced COW file system, its removal from upcoming kernels, and the broader implications for Linux’s storage stack.

BcachefsCOW filesystemLinus Torvalds

0 likes · 7 min read

Why bcachefs Was Dropped from Linux 6.17 – Linus’s Fury and COW Outlook

Jul 23, 2025 · Operations

What New Features Does Ubuntu 25.10 “Questing Quokka” Introduce?

Ubuntu 25.10 “Questing Quokka”, the final non‑LTS release before 26.04 LTS, brings GNOME 49, Wayland VRR, a Rust‑based sudo replacement, Dracut boot, RISC‑V spec updates, Microsoft Entra ID integration and a Linux 6.16 kernel, reshaping both desktop and enterprise experiences.

DracutEntra IDGNOME 49

0 likes · 4 min read

What New Features Does Ubuntu 25.10 “Questing Quokka” Introduce?

Architects' Tech Alliance

Jun 9, 2025 · Fundamentals

How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets

This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.

ARMCISCCPU architecture

0 likes · 12 min read

How Do x86, ARM, and RISC‑V Architectures Differ? A Deep Dive into CPU Instruction Sets

Architects' Tech Alliance

May 18, 2025 · Industry Insights

How Alibaba’s Chip Innovations Are Shaping AI, Cloud, and Edge Computing

This article provides a comprehensive technical analysis of Alibaba’s chip portfolio—including the XuanTie RISC‑V processors, Hanguang 800 AI accelerator, Yitian 710 server silicon, and a novel compute‑in‑memory architecture—detailing their specifications, performance highlights, roadmap plans, and real‑world applications in cloud, AI, and IoT ecosystems.

AI acceleratorAlibabaCompute-in-Memory

0 likes · 16 min read

How Alibaba’s Chip Innovations Are Shaping AI, Cloud, and Edge Computing

Mar 18, 2025 · Backend Development

What’s New in GCC 15? COBOL Frontend, C23 Default, and RISC‑V Boosts

GCC 15 is slated for release in late April or early May, bringing a native COBOL frontend, default C23 support, early C++23/26 features, expanded RISC‑V capabilities, and a roadmap that still leaves Algol‑68 for future versions.

Algol68C++23C23

0 likes · 6 min read

What’s New in GCC 15? COBOL Frontend, C23 Default, and RISC‑V Boosts

Open Source Linux

Feb 18, 2025 · Frontend Development

Run Linux Inside a PDF: How a Teen Turned a PDF into a Live OS

A teenage developer has ingeniously run a full Linux system inside a PDF by adapting the TinyEMU RISC‑V emulator to asm.js and using PDF‑embedded JavaScript, enabling interactive command‑line access via a virtual keyboard in Chromium‑based browsers.

PDFRISC-VTinyEMU

0 likes · 3 min read

Run Linux Inside a PDF: How a Teen Turned a PDF into a Live OS

IT Services Circle

Jan 9, 2025 · Fundamentals

Why the Best‑Performing Open‑Source CPU Is Chinese: The XiangShan Project

The XiangShan open‑source RISC‑V processor, praised for its ARM‑level performance and detailed micro‑architecture, has sparked worldwide discussion after a George Hotz tweet, highlighting China’s systematic development of a high‑performance, community‑driven CPU project that began in 2019 and continues to evolve.

ChinaRISC-VXiangShan

0 likes · 9 min read

Why the Best‑Performing Open‑Source CPU Is Chinese: The XiangShan Project

Architects' Tech Alliance

Dec 5, 2024 · Artificial Intelligence

Flex‑RV: An Open‑Source Sub‑$1 Flexible RISC‑V Microprocessor with Integrated Machine‑Learning Accelerator

The article presents Flex‑RV, a sub‑dollar, bendable 32‑bit RISC‑V microprocessor built with IGZO TFT technology that integrates a programmable machine‑learning accelerator, achieves up to 60 kHz operation at less than 6 mW, and demonstrates reliable performance under mechanical stress for emerging wearable and smart‑packaging applications.

IGZO TFTRISC-Vflexible electronics

0 likes · 21 min read

Flex‑RV: An Open‑Source Sub‑$1 Flexible RISC‑V Microprocessor with Integrated Machine‑Learning Accelerator

OPPO Kernel Craftsman

Nov 1, 2024 · Fundamentals

Highlights of the 19th China Linux Kernel Developers Conference (CLK 2024)

The 19th China Linux Kernel Developers Conference in Wuhan on October 26, 2024 attracted over 80,000 online viewers and nearly 400 developers, showcased five technical sub‑forums—from memory and storage I/O to virtualization and scheduling—featured AI‑focused kernel talks, announced a new open‑source innovation institute, and made all materials publicly available on GitHub.

AILinux kernelRISC-V

0 likes · 9 min read

Highlights of the 19th China Linux Kernel Developers Conference (CLK 2024)

Architects' Tech Alliance

Oct 9, 2024 · Industry Insights

Why Do x86, ARM, and RISC‑V Dominate Modern CPUs? A Deep ISA Comparison

This article compares the major instruction set architectures—x86, ARM, and RISC‑V—explaining their CISC versus RISC philosophies, historical evolution, technical trade‑offs, and the current market landscape of domestic and global CPU vendors.

ARMCPUInstruction Set

0 likes · 13 min read

Why Do x86, ARM, and RISC‑V Dominate Modern CPUs? A Deep ISA Comparison

Linux Code Review Hub

Aug 4, 2024 · Fundamentals

Why RISC‑V’s Integer ISA Omits a Multiply‑Accumulate Instruction – A Microarchitectural Guess

The article speculates why the RISC‑V integer ISA does not define a multiply‑accumulate (MAC) instruction, examining how such an instruction would affect integer‑unit micro‑architecture, decoder width, rename complexity, and OoO window size, and compares these trade‑offs with ARM and Apple M1 designs.

ARMApple M1ISA

0 likes · 6 min read

Why RISC‑V’s Integer ISA Omits a Multiply‑Accumulate Instruction – A Microarchitectural Guess

Jul 6, 2024 · Fundamentals

Linux 6.10 Adds Rust Support for RISC‑V Architecture

The latest Linux 6.10 merge introduces Rust language support for the RISC‑V architecture and expands Qualcomm Snapdragon X Elite features such as DisplayPort and eDP, while also noting a brief autumn recruitment reminder.

6.10LinuxRISC-V

0 likes · 2 min read

Linux 6.10 Adds Rust Support for RISC‑V Architecture

Apr 22, 2024 · Information Security

Linus Torvalds on Security, AI Hype, and the Future of Open‑Source Trust

During a candid “fireside chat” at the Linux Foundation North America Open Source Summit, Linus Torvalds discusses the challenges of hardware bugs, security vulnerabilities, AI hype, RISC‑V concerns, and the importance of trust and community in sustaining Linux’s open‑source ecosystem.

AILinuxRISC-V

0 likes · 9 min read

Linus Torvalds on Security, AI Hype, and the Future of Open‑Source Trust

Architects' Tech Alliance

Feb 11, 2024 · Fundamentals

Overview of Modern Processor Instruction Set Architectures: x86, ARM, and RISC‑V

This article provides a comprehensive overview of contemporary processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their design philosophies, historical evolution, advantages, disadvantages, and the current landscape of domestic and international CPU development.

ARMCISCInstruction Set Architecture

0 likes · 14 min read

Overview of Modern Processor Instruction Set Architectures: x86, ARM, and RISC‑V

Architects' Tech Alliance

Dec 11, 2023 · Fundamentals

Overview of Modern Processor Instruction Set Architectures: x86, ARM, and RISC‑V

This article provides a comprehensive overview of modern processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their historical development, design philosophies, advantages, disadvantages, and current market adoption in both domestic and global contexts.

ARMCISCISA

0 likes · 12 min read

Overview of Modern Processor Instruction Set Architectures: x86, ARM, and RISC‑V

Nov 4, 2023 · R&D Management

Who Leads the Global Open‑Source Revolution? Inside the First Worldwide Contribution Rankings

Bench Council unveiled the world’s first open‑source contribution ranking, highlighting 264 top contributors—including 24 Chinese—while showing the United States leading the national list, China second, and spotlighting seminal figures like Stallman, Perens, and Asanovic along with key institutions and projects such as RISC‑V and OpenBLAS.

Global RankingsRISC-Vbench council

0 likes · 4 min read

Who Leads the Global Open‑Source Revolution? Inside the First Worldwide Contribution Rankings

OPPO Kernel Craftsman

Sep 22, 2023 · Fundamentals

18th China Linux Kernel Developer Conference (CLK 2023) Call for Papers

The 18th China Linux Kernel Developer Conference (CLK 2023) will be held in Shenzhen on October 28, 2023, hosted by OPPO, and invites Linux kernel developers to submit technical papers (open call from September 22, deadline October 10) on topics such as architecture, scheduling, memory, storage, networking, virtualization, performance, testing and kernel use in IoT, mobile, automotive, cloud and AI, with required author bio, title and abstract.

CLK 2023RISC-Varm64

0 likes · 4 min read

18th China Linux Kernel Developer Conference (CLK 2023) Call for Papers

Jun 30, 2023 · Artificial Intelligence

How AI Created the World’s First Fully Autonomous CPU – Qǐ Méng 1

Chinese researchers used generative AI to design Qǐ Méng 1, the first completely self‑generated CPU chip that runs Linux and rivals early Intel 486 performance, showcasing the rapid rise of AI‑driven semiconductor design.

AICPURISC-V

0 likes · 4 min read

How AI Created the World’s First Fully Autonomous CPU – Qǐ Méng 1

Architects' Tech Alliance

Apr 27, 2023 · Industry Insights

What Drives China’s Emerging CPU Landscape? A Deep Dive into Six Domestic Chipmakers

This article examines China’s domestic CPU market, profiling six manufacturers, comparing their architectures (ARM, x86, LoongArch, RISC‑V, Alpha), detailing technical specifications, performance benchmarks, ecosystem support, and the impact of national programs on their development.

ARMChinese CPUsLoongArch

0 likes · 15 min read

What Drives China’s Emerging CPU Landscape? A Deep Dive into Six Domestic Chipmakers

Architects' Tech Alliance

Mar 9, 2023 · Artificial Intelligence

In‑Depth Analysis of Tesla D1 Processor and Dojo Architecture

This article provides a comprehensive technical review of Tesla's D1 AI processor and Dojo super‑computer architecture, covering its data‑flow near‑memory design, RISC‑V‑like instruction set, matrix compute units, chiplet packaging, power‑management, cooling solutions, and the associated software compilation ecosystem.

AI chipCompilation EcosystemDojo Architecture

0 likes · 23 min read

In‑Depth Analysis of Tesla D1 Processor and Dojo Architecture

Architects' Tech Alliance

Jan 28, 2023 · Fundamentals

2023 Semiconductor Industry Outlook: Ten Major Trends and Predictions

The 2023 semiconductor industry report forecasts ten key trends, including the dominance of mature process expansion, intensified policy environments, the rise of chiplet technology, FD‑SOI advancements, RISC‑V CPU IP breakthroughs, anti‑globalization shifts, front‑end integration by device makers, smart cockpit evolution, inventory cycle dynamics, and the push toward a fully domestic semiconductor ecosystem.

Chip manufacturingChipletFD-SOI

0 likes · 19 min read

2023 Semiconductor Industry Outlook: Ten Major Trends and Predictions

Laravel Tech Community

Dec 12, 2022 · Fundamentals

Go 1.20 Release Candidate Highlights: New Slice‑to‑Array Conversion, Unsafe Package Functions, and Comparable Types

Go 1.20 RC1 introduces experimental RISC‑V/FreeBSD support, expands slice‑to‑array conversion, adds three new unsafe package functions, updates comparable type constraints, and changes struct value comparison order, while being the final version compatible with macOS 10.13/10.14, with download details provided.

ComparableProgramming LanguageRISC-V

0 likes · 4 min read

Go 1.20 Release Candidate Highlights: New Slice‑to‑Array Conversion, Unsafe Package Functions, and Comparable Types

Architects' Tech Alliance

Dec 10, 2022 · Fundamentals

Comprehensive Overview of System-on-Chip (SoC) Architecture, History, and Market Trends

This article provides a detailed introduction to System-on-Chip (SoC) technology, covering its definition, component hierarchy, IP‑core concepts, historical milestones, typical architectures, instruction‑set families, AI‑enabled variants, and current market dynamics across mobile, server, and high‑performance computing domains.

AIRISC-VSOC

0 likes · 10 min read

Comprehensive Overview of System-on-Chip (SoC) Architecture, History, and Market Trends

Architects' Tech Alliance

Nov 14, 2022 · Fundamentals

2022 Chinese Server CPU Research Framework: Market Analysis and Architectural Trends

The article provides a comprehensive analysis of the 2022 CPU industry chain, market size, global landscape, and major vendors, covering the dominance of x86, the rise of ARM, Intel and AMD market dynamics, UMA attempts, and emerging architectures such as RISC‑V and Apple’s M1.

AMDARMCPU

0 likes · 14 min read

2022 Chinese Server CPU Research Framework: Market Analysis and Architectural Trends

Oct 3, 2022 · Fundamentals

What’s New in Linux Kernel 6.0? Key Features and Improvements Explained

Linux kernel 6.0, released on October 2 by Linus Torvalds, brings major enhancements such as Rust support, ARM and RISC‑V improvements, CPU fault detection, better ACPI power management, SMB3 performance, Intel Arc GPU certification, and even Atari PC optimizations, marking it as one of the most commit‑heavy releases in recent history.

6.0ARMLinux

0 likes · 4 min read

What’s New in Linux Kernel 6.0? Key Features and Improvements Explained

Architects' Tech Alliance

Aug 19, 2022 · Fundamentals

Analysis of China's Domestic CPU Industry and Future Outlook

This report examines the rapid development, challenges, and future prospects of China's domestic CPU industry, covering market growth, technological breakthroughs, ecosystem building, and strategic considerations for manufacturers and policymakers in the global context.

CPUChinaDomestic semiconductor

0 likes · 13 min read

Analysis of China's Domestic CPU Industry and Future Outlook

Aug 15, 2022 · Fundamentals

Why Linux Skipped 5.20 for 6.0 – Major Updates and Hidden Details

The article explains Linus Torvalds' decision to label the next Linux kernel release as 6.0 instead of 5.20, outlines the major code additions—including support for AMD GPUs, Intel Habana Gaudi2, RISC‑V, and new power‑management features—while noting missing Rust patches and performance improvements.

AMDIntelLinux

0 likes · 7 min read

Why Linux Skipped 5.20 for 6.0 – Major Updates and Hidden Details

Architects' Tech Alliance

Jun 19, 2022 · Fundamentals

Introduction to the RISC‑V Open Instruction Set Architecture

This article provides a comprehensive overview of RISC‑V, covering its open‑source ISA philosophy, historical development, RISC versus CISC design trade‑offs, modular extensions, basic integer instruction set, register file, common extensions such as M, F, D, C, and examples of commercial implementations, illustrating why RISC‑V has become a leading architecture for modern processors.

Instruction Set ArchitectureOpen ISARISC-V

0 likes · 10 min read

Introduction to the RISC‑V Open Instruction Set Architecture

Architects' Tech Alliance

May 16, 2022 · Fundamentals

MIPS Announces RISC‑V Based eVocore P8700 and I8500 Multi‑Processor IP Cores

MIPS Tech has shifted from its legacy CPU architecture to RISC‑V, unveiling the high‑performance, scalable eVocore P8700 and power‑efficient I8500 multi‑processor IP cores aimed at high‑performance, real‑time applications such as networking, data centers, automotive, and edge computing.

High PerformanceMIPSRISC-V

0 likes · 7 min read

MIPS Announces RISC‑V Based eVocore P8700 and I8500 Multi‑Processor IP Cores

Apr 25, 2022 · Backend Development

What New Features Will JDK 19 Bring? Exploring Vector API and RISC‑V Support

JDK 19, slated for release on September 20, will focus on two major proposals—a fourth‑generation Vector API for expressive vector computations and a port of the JDK to the open‑source Linux/RISC‑V RV64GV architecture—while continuing the short‑term release cadence and outlining upcoming timelines.

JDK 19JavaRISC-V

0 likes · 4 min read

What New Features Will JDK 19 Bring? Exploring Vector API and RISC‑V Support

Mar 28, 2022 · Backend Development

What Java Trends Will Shape 2022? From LTS Migration to Cloud and Security

This article examines the major Java trends for 2022, including the push to migrate from Java 8 to newer LTS releases, improved cloud and container support, multi‑platform advancements, security lessons from Log4Shell, and upcoming features in Java 18.

JavaLTSRISC-V

0 likes · 10 min read

What Java Trends Will Shape 2022? From LTS Migration to Cloud and Security

Architects' Tech Alliance

Mar 10, 2022 · Fundamentals

Why RISC‑V Is Succeeding: Open Architecture, Freedom, and Market Forces

The article explains how RISC‑V’s open, customizable ISA, the shift toward free and unrestricted hardware design, and market pressures such as Moore’s law slowdown and AI‑driven compute demand together fuel its rapid adoption, ecosystem growth, and competitive edge over proprietary architectures.

Hardware InnovationOpen ISARISC-V

0 likes · 11 min read

Why RISC‑V Is Succeeding: Open Architecture, Freedom, and Market Forces

Architects' Tech Alliance

Jan 21, 2022 · Industry Insights

Why ARM Is Overtaking X86: A Deep Dive into CPU Architecture Trends

An extensive analysis traces the evolution of CPU architectures—from early Intel 4004 to modern x86, ARM, RISC‑V and MIPS—examining their technical differences, market shares, recent performance gains, and the shifting competitive landscape across servers, desktops, mobile devices, and emerging IoT applications.

ARMCPU architectureRISC-V

0 likes · 18 min read

Why ARM Is Overtaking X86: A Deep Dive into CPU Architecture Trends

Dec 9, 2021 · Artificial Intelligence

How Alibaba’s DAMO Academy Is Redefining AI with the First 3D‑Stacked Compute‑Memory Chip

On December 3, Alibaba’s DAMO Academy announced its first AI chip that integrates memory and compute using hybrid‑bond 3D stacking, promising ten‑fold performance gains and 300× energy efficiency for AI workloads such as recommendation systems, and marking a shift from traditional von Neumann designs.

3D stackingAI chipCompute-in-Memory

0 likes · 5 min read

How Alibaba’s DAMO Academy Is Redefining AI with the First 3D‑Stacked Compute‑Memory Chip

Architects' Tech Alliance

Oct 16, 2021 · Fundamentals

The New Golden Age of Computer Architecture: Trends, Challenges, and Opportunities

This article reviews the historical evolution of computer architecture, analyzes the end of Dennard scaling and Moore's Law, discusses domain‑specific architectures, open ISAs like RISC‑V, security vulnerabilities, and emerging opportunities such as agile hardware development and specialized accelerators.

Performance ScalingRISC-Vdomain-specific architectures

0 likes · 41 min read

The New Golden Age of Computer Architecture: Trends, Challenges, and Opportunities

Architects' Tech Alliance

Sep 30, 2021 · Industry Insights

What Drives the Global CPU Landscape? From Intel’s Legacy to ARM’s Rise

This article provides a comprehensive analysis of CPU architecture evolution, workflow, historical milestones, CISC versus RISC competition, the emergence of RISC‑V, China's domestic processor initiatives, and current market share trends across servers, desktops, and mobile devices.

ARMCPURISC-V

0 likes · 18 min read

What Drives the Global CPU Landscape? From Intel’s Legacy to ARM’s Rise

Architects' Tech Alliance

Aug 24, 2021 · Fundamentals

A New Golden Age for Computer Architecture: Trends, Challenges, and Opportunities

This article reviews the evolution of computer architecture, discusses the end of Dennard scaling and Moore’s law, highlights the rise of domain‑specific and RISC‑V designs, examines security challenges, and outlines future opportunities for more efficient, open, and agile hardware solutions.

RISC-Vagile hardware developmentdomain-specific architectures

0 likes · 41 min read

A New Golden Age for Computer Architecture: Trends, Challenges, and Opportunities

Architects' Tech Alliance

Apr 2, 2021 · Fundamentals

MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.

Instruction Set ArchitectureMIPSOpen ISA

0 likes · 9 min read

MIPS Open Instruction Set (Release 6) Initiative and Comparison with RISC‑V

Architects' Tech Alliance

Mar 15, 2021 · Fundamentals

Understanding RISC‑V and Open‑Source Processors: Clarifying Misconceptions and Architectural Basics

This article clarifies common misunderstandings about RISC‑V and open‑source processors by explaining the distinction between instruction set specifications and implementations, the openness of the ISA, commercial versus open‑source micro‑architectures, and the geopolitical aspects of RISC‑V adoption.

Hardware FundamentalsRISC-Vopen-source processors

0 likes · 12 min read

Understanding RISC‑V and Open‑Source Processors: Clarifying Misconceptions and Architectural Basics

Architects' Tech Alliance

Mar 10, 2021 · Industry Insights

Why RISC‑V Is Shaping the Future of Custom Chips in China and Beyond

The article analyzes RISC‑V’s open, modular ISA, its technical advantages over legacy architectures, the rapidly maturing global and Chinese ecosystems, real‑world applications, and strategic recommendations for China to build an independent, competitive semiconductor industry amid trade tensions and policy drives.

AI HardwareChina technology policyIoT

0 likes · 10 min read

Why RISC‑V Is Shaping the Future of Custom Chips in China and Beyond

Architects' Tech Alliance

Jan 24, 2021 · Fundamentals

RISC‑V Instruction Set Architecture: Background, Technical Features, Ecosystem, and Industry Applications

The article provides a comprehensive overview of RISC‑V, covering its origins amid trade‑war pressures, open‑source technical characteristics, growing global and Chinese ecosystem, comparisons with ARM and x86, and its emerging role in low‑power, customizable chips for IoT and AI applications.

AIInstruction Set ArchitectureIoT

0 likes · 10 min read

RISC‑V Instruction Set Architecture: Background, Technical Features, Ecosystem, and Industry Applications

Architects' Tech Alliance

Jan 18, 2021 · Fundamentals

RISC‑V: A Lightweight Instruction Set for the Heterogeneous IoT Era

The article introduces three major instruction‑set families—CISC (x86), RISC (ARM) and the ultra‑lightweight RISC‑V—explaining how RISC‑V, as the fifth‑generation RISC architecture, balances data throughput and speed, making it an ideal, self‑controlled solution for China’s AI and IoT development despite its still‑growing ecosystem.

AIInstruction Set ArchitectureIoT

0 likes · 2 min read

RISC‑V: A Lightweight Instruction Set for the Heterogeneous IoT Era

Architects' Tech Alliance

Dec 21, 2020 · Fundamentals

RISC‑V Architecture: History, Advantages, and Emerging Applications

The article provides a comprehensive overview of the open‑source RISC‑V instruction set, its historical development, technical benefits such as modularity and a minimal instruction set, and its growing relevance across IoT, mobile, server, storage, AI, and security domains, while also discussing ecosystem challenges and industry initiatives.

CPU architectureIoTRISC-V

0 likes · 12 min read

RISC‑V Architecture: History, Advantages, and Emerging Applications

Aug 9, 2020 · Fundamentals

How Five Undergraduates Designed a 64‑bit RISC‑V Chip and Graduated with Their Own Processor

Five 2016‑class undergraduates from the University of Chinese Academy of Sciences completed a 64‑bit RISC‑V SoC chip named "NutShell," successfully fabricated it in 110 nm, ran Linux and a custom teaching OS, and presented the open‑source design at the RISC‑V Global Forum, showcasing a novel "One Life One Chip" education model.

RISC-VSOCchip design

0 likes · 19 min read

How Five Undergraduates Designed a 64‑bit RISC‑V Chip and Graduated with Their Own Processor

Architects' Tech Alliance

Jun 22, 2019 · Fundamentals

Illustrated Full Process of Intel Core i7 CPU Production and Architecture Overview

This article provides a comprehensive, illustrated guide to the entire manufacturing workflow of an Intel Core i7 CPU—from raw silicon extraction and purification, through photolithography, doping, and multilayer metal deposition, to testing, packaging, and future architectural outlooks including x86 limitations and the rise of RISC‑V and the RIOS lab.

CPUIntelRISC-V

0 likes · 27 min read

Illustrated Full Process of Intel Core i7 CPU Production and Architecture Overview

Architects' Tech Alliance

Jun 2, 2019 · Fundamentals

MIPS Goes Open Source: Wave Computing’s Strategy and Industry Implications

Wave Computing announced the open‑source release of the MIPS ISA and its R6 core in early 2019, positioning MIPS as a commercial‑ready alternative to RISC‑V while addressing ecosystem challenges, patent issues, and market dynamics in China and beyond.

AIInstruction Set ArchitectureMIPS

0 likes · 10 min read

MIPS Goes Open Source: Wave Computing’s Strategy and Industry Implications

Architects' Tech Alliance

May 22, 2019 · Fundamentals

The Rise of RISC‑V: Open‑Source ISA Adoption, Industry Momentum, and Future Challenges

RISC‑V, an open‑source instruction set architecture created at UC Berkeley, is rapidly gaining support from major tech companies, academic institutions, and governments worldwide because of its low cost, flexible licensing, and potential to become the Linux‑like foundation for CPUs, though concerns about fragmentation and lack of a strong steward remain.

CPU architectureRISC-Vhardware

0 likes · 10 min read

The Rise of RISC‑V: Open‑Source ISA Adoption, Industry Momentum, and Future Challenges

Architects' Tech Alliance

Dec 25, 2018 · Fundamentals

MIPS Goes Open Source: Wave Computing’s Strategy and Industry Implications

Wave Computing announced that the MIPS instruction set architecture and its latest R6 core will be released as open source in early 2019, sparking industry debate about the move’s impact on MIPS’s market position, licensing revenue, and competition with RISC‑V, especially in the AI and Chinese markets.

MIPSRISC-VWave Computing

0 likes · 11 min read

MIPS Goes Open Source: Wave Computing’s Strategy and Industry Implications

Architects' Tech Alliance

May 9, 2018 · Fundamentals

The Rise of RISC‑V: Open‑Source Instruction Set Architecture and Its Growing Adoption

RISC‑V, an open‑source, BSD‑licensed instruction set architecture created at UC Berkeley, is gaining rapid adoption worldwide as companies and governments seek a cost‑free, flexible alternative to costly ARM and x86 licenses, driving a surge in processor development, academic research, and ecosystem growth.

CPU architectureRISC-Vopen-source ISA

0 likes · 10 min read

The Rise of RISC‑V: Open‑Source Instruction Set Architecture and Its Growing Adoption