Overview of ASIC Chips: Types, Characteristics, and Applications

ASIC (Application Specific Integrated Circuit) Overview ASIC chips are custom‑designed integrated circuits tailored to specific electronic system requirements, offering optimized computational efficiency for algorithms such as AI, cryptocurrency mining, printing, and defense applications.

Hardware Composition At the material level, ASICs use silicon, gallium phosphide, gallium arsenide, or nitride substrates. Physically, they integrate IP cores like external storage, power managers, audio‑visual processors, and network circuits, with one or multiple ASIC modules on a single board to meet varied functional needs.

ASIC Classification

(1) By Customization Degree

• Full‑custom ASIC – highest customization, designing logic units, analog circuits, storage, and mechanical structures; mask‑based interconnections; design time >9 weeks, high performance and power efficiency.

• Semi‑custom ASIC – combines standard cell libraries with custom logic; lower cost and higher flexibility; includes gate‑array and standard‑cell sub‑types.

• Programmable ASIC – encompasses FPGA and PLD devices; PLDs consist of logic matrices, flip‑flops, and interconnects programmable for specific applications.

(2) By Terminal Function

• TPU (Tensor Processing Unit) – dedicated to machine‑learning workloads, e.g., Google’s AI accelerator.

• BPU (Brain Processing Unit) – Horizon Robotics’ embedded AI processor architecture.

• NPU (Neural Processing Unit) – mimics neural networks with deep‑learning instruction sets for large‑scale neuron and synapse data processing.

Full‑Custom ASIC Details Designed from scratch with bespoke logic units, masks, and structures; offers superior performance (up to 8× the compute of semi‑custom ASICs) and lower power consumption, though with higher design cost and longer development cycles.

Semi‑Custom ASIC Details Utilizes standard cell libraries and custom logic; subdivided into:

• Gate‑array ASIC – includes channel, channel‑less, and structured gate arrays, where transistor placement is fixed and interconnects are adjusted via metal layers.

• Standard‑cell ASIC – built from selected standard cells, allowing designers to arrange cells per algorithmic needs; may also incorporate fixed blocks like microcontrollers.

Programmable ASIC Details Covers FPGA and PLD devices; PLDs consist of logic matrices, registers, and interconnects programmable to meet partial custom requirements.

ASIC Chip Characteristics

Advantages

• Area Efficiency – eliminates redundant logic, enabling smaller die sizes and higher wafer yield.

• Power Efficiency – ASICs consume roughly 0.2 W per compute unit versus 0.4 W for GPUs.

• Integration – highly integrated design yields high‑performance circuits.

• Cost – lower unit price (average ≈ $3) with potential further reductions at mass production.

Disadvantages

• Long design cycles and high development cost due to extensive physical and reliability verification.

• Strong algorithm dependency; rapid AI algorithm updates can outpace ASIC revisions.

• Market risk – long time‑to‑market increases chance of obsolescence.

Notable ASIC Products

• Google TPU (2016) – integrated in AlphaGo and cloud AI services.

• IBM TrueNorth (28 nm, 2014) – brain‑inspired chip for real‑time video processing.

• Intel Xeon ASIC series (2017) – standalone processors for deep‑learning workloads.

• Stanford neuromorphic ASIC – 9,000× speedup over conventional PCs, simulating ~1 million neurons.

• Emerging startups applying ASICs to security, ADAS, consumer electronics, and medical devices.

Market Outlook in China

Growth drivers include edge‑computing AI demand, consumer electronics (AR/VR, drones, smart home), graphics‑based deep‑learning processors, and the rise of AI terminals capable of both training and inference, projecting widespread ASIC adoption by 2022.

Reference: China ASIC Chip Industry Premium Report.