Overview of Huawei Kunpeng 920 Processor Architecture and Subsystems

1. Organization of Kunpeng Processor

In Kunpeng terminology, a Chip is a silicon package containing one or more dies. A Die is the smallest physical unit; Kunpeng 920 packages three dies: two compute dies and one I/O die.

A Core is the actual processing unit seen by the operating system. A Cluster groups four cores, and each compute die contains eight clusters, giving a total of 64 cores (2 dies × 8 clusters × 4 cores).

The SoC (System on Chip) integrates the CPU cores together with network, storage, and other peripheral controllers, effectively providing a complete system on a single silicon piece.

2. Kunpeng 920 Chip Architecture

The SoC consists of three dies: two compute dies and one I/O die. Each compute die contains eight clusters, each cluster contains four cores, resulting in 64 cores overall. Each core has private L1 and L2 caches, while all cores share an L3 cache. The I/O die integrates network and PCIe modules, and the dies are interconnected via a high‑speed internal bus.

3. System Security & IMU

The platform supports Secure Boot and ARM TrustZone to ensure a trusted execution environment. The Intelligent Management Unit (IMU) provides data‑center node management, fault pre‑processing, error reporting, trust root, and power‑efficiency management, working together with BMC for coordinated monitoring.

4. Other Subsystems of Kunpeng 920

The processor includes compute, storage, I/O, interrupt, and virtualization subsystems. It features two CPU dies, one I/O die, and eight DDR4 channels, all interconnected via the AMBA bus.

5. I/O Subsystem

The I/O die extends the SoC with accelerators such as 100 GbE NICs and SAS controllers, and supports PCIe 4.0 for GPUs, NICs, and other expansion cards. All high‑speed devices are accessible via PCIe configuration space.

6. Interrupt Subsystem

The processor implements an ARM‑compatible Generic Interrupt Controller (GIC) with support for level, message, and LPI (Locality‑specific Peripheral Interrupt) types. Features include enabling/disabling SGI, PPI, SPI, LPI; routing interrupts to any CPU core; priority configuration; and AArch64 security and virtualization extensions. It also introduces interrupt collection and redistribution, and Huawei’s MBIGEN technology.

7. Network Subsystem

The network subsystem comprises a Network ICL and a RoCE engine. The ICL provides multiple Ethernet controllers (1 Gbps–100 Gbps), DCB, MAC tables, VLAN filtering, flow tables, and PCIe integration. RoCE v2 offers low‑latency, low‑CPU‑utilization RDMA over Ethernet.

8. SAS Subsystem

Kunpeng 920 includes two X8 SAS 3.0 controllers, supporting SAS 3.0, SAS 2.0, SAS 1.0, SATA 3.0, and various data rates (12 G/6 G/3 G/1.5 G for SAS, 6 G/3 G/1.5 G for SATA). It can directly connect up to eight SAS or SATA drives, supports both direct and expander connections, and includes NOR, SPI, and NAND flash controllers.

9. PCIe Subsystem

The PCIe subsystem supports Gen1/2/3/4.0, running at 2.5 GT/s, 5 GT/s, 8 GT/s, or 16 GT/s, with up to 40 lanes across three PCIe cores (Core0 × 16 lanes, Core1 × 16 lanes, Core2 × 8 lanes). Features include embedded DMA engines, SR‑IOV, shared virtual memory, CCIX, and peer‑to‑peer traffic.

Source: Huawei Cloud Community