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The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster layout, security features, IMU management, and the various subsystems such as IO, interrupt, network, SAS, and PCIe.
The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster hierarchy, security features, and the various compute, I/O, interrupt, network, SAS, and PCIe subsystems integrated on the SoC.
The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cache hierarchy, security features, IMU management, and the design of its I/O, interrupt, network, SAS, and PCIe subsystems.
This article provides a detailed introduction to System-on-Chip (SoC) technology, covering its definition, component hierarchy, IP‑core concepts, historical milestones, typical architectures, instruction‑set families, AI‑enabled variants, and current market dynamics across mobile, server, and high‑performance computing domains.
The article outlines ARM TrustZone‑enabled SoC components and the CryptoCell architecture, describing its two product families (700 and 300), hardware modules for symmetric and asymmetric cryptography, secure key slots, the CRYS software library, and their roles in secure‑boot, lifecycle management, debugging and data protection.
This article details the challenges, design choices, deployment steps, detection model creation, data processing, visualization, and future plans of JD Daojia's security operations platform, highlighting the use of Graylog, Elasticsearch, and MongoDB to achieve scalable, real‑time threat detection and response.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
The article explains how mobile processors prioritize low power, heat, and voltage while improving performance, compares RISC and CISC architectures, discusses the X86‑ARM rivalry, and outlines the rise of heterogeneous System‑on‑Chip designs and their expanding applications across consumer electronics.
The Intelligent Power Allocation (IPA) governor, introduced in Linux kernel 4.2, uses a PID‑based closed‑loop controller and a dynamic power allocator to distribute sustainable power among CPU, GPU and other IP cores, maximizing performance while respecting temperature limits, but requires careful PID tuning and device‑tree configuration.
CPU power consumption comprises static leakage and dynamic switching energy, so modern SoCs use low‑power C‑states and core‑control isolation to shut down idle cores, with the kernel’s corectl module dynamically evaluating load and task counts each scheduler tick to decide how many CPUs to activate or deactivate, configurable via sysfs.
The article provides a comprehensive overview of DDR5 DRAM technology, detailing its higher density, lower voltage, increased data rates, enhanced reliability features, and its suitability for servers, cloud computing, networking, laptops, desktops, and consumer SoC applications.
This article explains why standardized log parsing is crucial for security analytics, outlines key parsing concepts, compares pre‑ and post‑parsing approaches, discusses flexible custom parsing methods, and offers practical guidance to improve accuracy and efficiency in large‑scale security environments.
This document outlines the background, challenges, and a comprehensive enterprise intrusion detection solution that combines host‑based and network‑based monitoring, automated CVE and GitHub leak collection, a modular agent‑middle‑display architecture, and future plans for multi‑dimensional threat modeling to enhance preventive security capabilities.
This article chronicles Huawei's journey from establishing an ASIC design center in 1991, founding HiSilicon in 2004, and developing a full portfolio of digital‑home, communication, and mobile SoC chips—including the Kirin series—while explaining the fabless model, ARM licensing, and industry impact.