This article breaks down the seven types of chips—GPU/AI accelerators, CPUs, SoCs, MCUs, power semiconductors, network/interconnect chips, and storage chips—that together form the hardware backbone of modern AI data centers, explaining each component's role, key technologies, and why they must work in concert.
The article compares SOC and MCU for embedded systems, using analogies, performance and power benchmarks, development ecosystem contrasts, and cost considerations to show how each fits different application requirements and why choosing the right one matters.
The article explains how Anthropic’s Claude Skills framework enables AI agents to execute expert-level cybersecurity tasks by organizing 734+ MITRE ATT&CK‑mapped skills, detailing their structure, progressive loading, real‑world workflows, deployment steps, customization, and the operational benefits for SOCs, detection engineers, and incident responders.
Espressif's upcoming ESP32‑S31 is a dual‑core RISC‑V wireless MCU featuring a high‑performance core with FPU/SIMD, a low‑power core, 62 GPIO, gigabit Ethernet, Wi‑Fi, Bluetooth, 802.15.4, plus a rich set of peripherals, while offering fewer multimedia interfaces than the ESP32‑P4.
At RSAC 2026, analysts warned that AI is reshaping cybersecurity into two simultaneous battles—rebuilding defenses with AI and protecting AI systems themselves—while attack timelines have collapsed from nine days to thirty minutes, forcing defenders to rethink SOC operations, architecture, and readiness.
As AI enables attackers to mass‑generate phishing emails and morph malware, traditional signature‑based defenses crumble, and the article explains how intent detection shifts security from static signatures to behavior‑based analysis, offering SOCs proactive alerts, reduced alert fatigue, and a way to counter AI‑driven attacks while acknowledging data quality, adversarial, and explainability challenges.
This report details a university big‑data project that builds a data‑driven framework for assessing lithium‑ion battery storage health, cleaning operational data, detecting abnormal cells with DBSCAN, and predicting SOC/SOH using LightGBM, while highlighting findings, limitations, and future improvements.
This article walks through practical Python data‑analysis steps for vehicle telemetry, covering data import, time‑based calculations, SOC efficiency metrics, speed binning, group aggregation, common coding pitfalls, and tips for clean, reproducible analysis using pandas.
The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster layout, security features, IMU management, and the various subsystems such as IO, interrupt, network, SAS, and PCIe.
The 2024 automotive cockpit SoC market analysis reveals that consumer‑grade chip makers like Qualcomm, AMD, and Samsung now lead in both cost efficiency and iteration speed, capturing over 90% of market share, while domestic Chinese suppliers lag behind but stand to grow as the industry expands.
The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cluster hierarchy, security features, and the various compute, I/O, interrupt, network, SAS, and PCIe subsystems integrated on the SoC.
The article provides a detailed technical overview of Huawei's Kunpeng 920 processor, describing its ARM‑based RISC architecture, chip organization, core and cache hierarchy, security features, IMU management, and the design of its I/O, interrupt, network, SAS, and PCIe subsystems.
This article provides a detailed introduction to System-on-Chip (SoC) technology, covering its definition, component hierarchy, IP‑core concepts, historical milestones, typical architectures, instruction‑set families, AI‑enabled variants, and current market dynamics across mobile, server, and high‑performance computing domains.
The article outlines ARM TrustZone‑enabled SoC components and the CryptoCell architecture, describing its two product families (700 and 300), hardware modules for symmetric and asymmetric cryptography, secure key slots, the CRYS software library, and their roles in secure‑boot, lifecycle management, debugging and data protection.
This article details the challenges, design choices, deployment steps, detection model creation, data processing, visualization, and future plans of JD Daojia's security operations platform, highlighting the use of Graylog, Elasticsearch, and MongoDB to achieve scalable, real‑time threat detection and response.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
The article explains how mobile processors prioritize low power, heat, and voltage while improving performance, compares RISC and CISC architectures, discusses the X86‑ARM rivalry, and outlines the rise of heterogeneous System‑on‑Chip designs and their expanding applications across consumer electronics.
This article explains the three JEDEC DRAM categories—Standard DDR, Mobile DDR (LPDDR), and Graphics DDR (GDDR/HBM)—detailing their architectures, performance characteristics, power requirements, and typical application domains such as servers, mobile devices, AI, and high‑throughput graphics.
The article defines System‑on‑Chip (SoC), outlines its key components and advantages, presents market size data showing rapid growth from 2017 to 2023, reviews the technology’s origins in the mid‑1990s, and highlights emerging trends such as the convergence of SoC, MEMS and SiP technologies.
The Intelligent Power Allocation (IPA) governor, introduced in Linux kernel 4.2, uses a PID‑based closed‑loop controller and a dynamic power allocator to distribute sustainable power among CPU, GPU and other IP cores, maximizing performance while respecting temperature limits, but requires careful PID tuning and device‑tree configuration.
CPU power consumption comprises static leakage and dynamic switching energy, so modern SoCs use low‑power C‑states and core‑control isolation to shut down idle cores, with the kernel’s corectl module dynamically evaluating load and task counts each scheduler tick to decide how many CPUs to activate or deactivate, configurable via sysfs.
This article traces Huawei’s three‑decade journey from its modest 1991 chip beginnings to a diversified portfolio of five major series—Kirin, Kunpeng, Ascend, Balong/Tiangang, Boudica/Lingxiao, and Honghu—detailing their technical evolution, market impact, and future roadmap across mobile, compute, AI, 5G, IoT, and video domains.
Five 2016‑class undergraduates from the University of Chinese Academy of Sciences completed a 64‑bit RISC‑V SoC chip named "NutShell," successfully fabricated it in 110 nm, ran Linux and a custom teaching OS, and presented the open‑source design at the RISC‑V Global Forum, showcasing a novel "One Life One Chip" education model.
The article provides a comprehensive overview of DDR5 DRAM technology, detailing its higher density, lower voltage, increased data rates, enhanced reliability features, and its suitability for servers, cloud computing, networking, laptops, desktops, and consumer SoC applications.
This article explains why standardized log parsing is crucial for security analytics, outlines key parsing concepts, compares pre‑ and post‑parsing approaches, discusses flexible custom parsing methods, and offers practical guidance to improve accuracy and efficiency in large‑scale security environments.
This document outlines the background, challenges, and a comprehensive enterprise intrusion detection solution that combines host‑based and network‑based monitoring, automated CVE and GitHub leak collection, a modular agent‑middle‑display architecture, and future plans for multi‑dimensional threat modeling to enhance preventive security capabilities.
This article chronicles Huawei's journey from establishing an ASIC design center in 1991, founding HiSilicon in 2004, and developing a full portfolio of digital‑home, communication, and mobile SoC chips—including the Kirin series—while explaining the fabless model, ARM licensing, and industry impact.
