Overview of the Specialized Data Processing Unit (DPU) Technology Whitepaper
The whitepaper from the Institute of Computing Technology, Chinese Academy of Sciences, provides a comprehensive analysis of DPU background, technical characteristics, reference architecture, application scenarios, and a comparative review of existing DPU products, highlighting its role in modern data‑center infrastructures.
Recently, the Institute of Computing Technology, Chinese Academy of Sciences, together with China Computer Federation and other partners, released the "Specialized Data Processing Unit (DPU) Technology Whitepaper," which analyzes DPU background, technical characteristics, reference architecture, application scenarios, and compares existing DPU products.
Part 1: Overview
This part defines DPU, describes its development background, historical evolution, role in the current computing ecosystem, and summarizes industrialization opportunities.
Part 2: DPU Architecture
It details the structural features of DPU, presents a five‑layer software‑stack model, surveys industry products, and proposes a generic DPU structural model.
Part 3: Application Scenarios
The whitepaper identifies three primary use cases: network function offload, storage function offload, and security function offload.
1. What is a DPU?
A DPU (Data Processing Unit) is a data‑centric specialized processor that supports infrastructure‑level virtualization, storage, security, and QoS management. Positioned by NVIDIA as the “third main chip” after CPU and GPU, DPU aims to offload workloads that CPUs handle inefficiently, reducing total cost of ownership.
1.1 Interpretation of “D”
(1) Data Processing Unit – focuses on processing various digital data such as tables, network packets, and massive text.
(2) Datacenter Processing Unit – emphasizes the datacenter as the primary deployment scenario.
(3) Data‑centric Processing Unit – reflects a design philosophy that places data, rather than control flow, at the core of the architecture.
1.2 Functions of DPU
DPU serves as a CPU offload engine for network virtualization, resource pooling, and security processing, freeing CPU cycles for higher‑level applications. It can act as a data gateway for encryption/decryption, a storage front‑end via NVMe‑oF, and a flexible accelerator platform integrating FPGA or programmable logic.
2. Development Background
Slowing Moore’s law and explosive data growth have created a performance gap between CPU capability and bandwidth demands, prompting the emergence of specialized chips like DPU.
Rapid expansion of network bandwidth (10G‑400G) and “new infrastructure” initiatives (5G, fiber, cloud) further stress CPU resources, making DPU a viable solution.
2.1 Bandwidth‑Performance Ratio Imbalance
Network bandwidth growth outpaces CPU performance growth, leading to a rising RBP (Ratio of Bandwidth and Performance) metric that highlights the need for dedicated processing units.
Figure 1‑1 shows the RBP trend.
2.2 Heterogeneous Computing Trend Support
DPU originated as a compute‑offload engine, similar to early TOE (TCP/IP Offload Engine) technologies, and has evolved through smart NIC generations to incorporate programmable cores, enabling flexible data‑plane and control‑plane processing.
Major cloud providers (AWS Nitro, Alibaba X‑Dragon, Intel IPU) have integrated DPU‑like accelerators to offload virtualization, networking, and storage tasks, achieving up to 30% CPU savings.
3. DPU Evolution
Smart NIC development is divided into three stages: basic NIC, hardware‑offload NIC, and DPU‑enabled smart NIC, each adding more compute capability and programmability.
3.1 Future Hardware Forms
Future DPU smart NICs may adopt (1) independently powered cards, (2) PCIe‑less resource‑pool cards, or (3) multi‑PCIe, multi‑port chips such as Fungible F1, offering up to 16 PCIe controllers and 8×100 Gbps network interfaces.
4. Relationship with CPU and GPU
CPU defines the general‑purpose computing ecosystem, GPU excels at data‑parallel workloads, while DPU targets infrastructure‑level, I/O‑intensive, and security‑critical tasks, complementing both and forming a balanced heterogeneous compute platform.
5. Industrial Opportunities
Major vendors (NVIDIA, Xilinx/Alveo, Intel, Marvell, etc.) have launched DPU product lines, and cloud giants (Google, Amazon, Alibaba) are developing their own DPU‑style chips. Market forecasts predict DPU shipments to reach hundreds of millions of units within five years, becoming as ubiquitous as network cards in servers.
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