The Rise of RISC‑V: Open‑Source ISA Adoption, Industry Momentum, and Future Challenges

Recently Tesla joined the RISC‑V Foundation and is considering using the free RISC‑V design in its next‑generation chips; more than 100 technology companies including IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google and Huawei have already become members.

One major driver is the high cost of ARM licensing; RISC‑V’s completely open instruction set, released under a permissive BSD license, makes it a strong candidate to become the "Linux of the CPU world" and has attracted many tech giants while the ISA was still a potential market.

Birth of RISC‑V

In 2010 a research team at the University of California, Berkeley set out to create a new ISA because X86 was tightly controlled by Intel, ARM licensing was expensive, and other ISAs such as MIPS, SPARC and PowerPC faced IP issues. The team decided to design an open ISA that could scale from micro‑controllers to super‑computers.

Within three months the team completed the first RISC‑V specification, which initially contained fewer than 50 instructions capable of fixed‑point arithmetic and privileged modes, while allowing users to add custom instructions as needed.

The name RISC‑V reflects a "Reduced Instruction Set Computer" (RISC) and the Roman numeral V, indicating the fifth generation, following Professor David Patterson’s earlier four‑generation processor designs.

Crucially, the ISA is released under the BSD open‑source license, allowing free use, modification, redistribution, and commercial exploitation—unlike ARM or PowerPC which require costly licenses. This freedom is similar to how Apple can build iOS on a BSD‑based kernel while keeping the final product proprietary.

Academic institutions have embraced RISC‑V; for example, a research team at the Chinese Academy of Sciences switched from the closed‑source OpenSPARC T1 and a non‑open processor to RISC‑V, later contributing technology used in Huawei’s HiSilicon ARM‑based server CPUs.

Because of its open and free nature, many commercial companies are now interested in RISC‑V, seeing it as a cost‑effective alternative to ARM.

RV12 RISC‑V Processor

RISC‑V aims to replicate Linux’s success: today X86 and ARM dominate CPUs, but both impose restrictive licensing—Intel limits X86 use to a few partners, and ARM’s fees are prohibitively high for many companies. This creates an opening for RISC‑V.

Companies such as Western Digital (planning to use a billion RISC‑V cores annually) and NVIDIA (integrating RISC‑V controllers into GPUs) have announced RISC‑V projects, while DARPA funds aerospace chips based on the ISA. The software ecosystem is also maturing, with toolchains, interrupt controllers, JVM, LLVM, Python, and other developer tools being ported to RISC‑V.

Open‑source and free licensing enable worldwide development of RISC‑V‑compatible processors without any royalty payments, giving the ISA a strong chance to become as ubiquitous as Linux.

Conclusion

RISC‑V is highly attractive to universities and research institutes and is expected to play a major role in education, creating a pipeline of talent for the industry. High ARM licensing costs also motivate commercial firms to adopt RISC‑V as a backup architecture.

However, a potential risk is the lack of a strong governing body, which could lead to fragmentation as companies add custom extensions—mirroring the historical split of MIPS into multiple variants. Without coordinated leadership, RISC‑V may struggle to compete with X86 and ARM at the highest levels.

Thanks to researcher Bao Yun‑gang from the Chinese Academy of Sciences for guiding this article.