TSMC 2026 Roadmap Reveals A12 (1.2nm), A13 (1.3nm) and N2U Nodes

On April 22, TSMC presented a four‑year roadmap (2026‑2029) at its North America Technology Forum, directly naming the upcoming A12 (1.2 nm) and A13 (1.3 nm) process nodes and introducing a new member of the N2 family, N2U. The most striking claim is that all new nodes through 2029 will be manufactured without the costly High‑NA EUV lithography system.

Strategic shift : Historically, TSMC’s most advanced processes were driven by mobile‑phone requirements—optimizing power, area and cost. The surge in AI, large‑model training, and high‑performance computing (HPC) has outpaced consumer‑device demand. Rather than a single "one‑size‑fits‑all" upgrade path, TSMC now splits its advanced node development into two parallel tracks:

Mobile track : Annual node refresh, emphasizing stability, cost‑effectiveness, and compatibility ("steady, cheap, fast iteration").

AI/HPC track : Biennial node refresh, prioritizing maximum performance regardless of cost ("strong, extreme, no limits").

For the mobile‑oriented track, the roadmap stresses "stability, cost, compatibility". All nodes—N2, N2P, the newly announced N2U, and the upcoming A14 (2028) and A13 (2029)—focus on IP reuse and design compatibility, delivering incremental energy‑efficiency gains with minimal design changes.

N2U details : Marketed as an "extended‑life" version of the N2 family, N2U offers 3‑4 % higher performance at the same power, 8‑10 % lower power at the same speed, and a 2‑3 % increase in logic density. Customers can adopt N2U without redesigning their chips, making it ideal for mid‑range product cycles.

A13 vs. A14 : A13 is described as a "refined" version of A14, using optical shrink to reduce chip area by about 6 %, with modest gains in density and energy efficiency while remaining fully compatible with existing IP, thus protecting earlier investments.

AI/HPC extreme‑performance lane : The upcoming A16 node will be the first to use the SPR (Super Power Rail) that moves the power delivery network to the backside of the die, freeing the front side for signal routing and solving the "power‑delivery bottleneck" of large‑scale AI chips.

Production timelines have been adjusted: the originally planned 2026 mass production of A16 is now pushed to large‑scale volume in 2027, aligning better with customer product cycles. The roadmap culminates in 2029 with the A12 node (1.2 nm), featuring second‑generation GAA nanosheets and NanoFlex Pro technology that simultaneously shrinks front‑ and backside dimensions, delivering a leap in performance, density, and power across all nodes and directly challenging the advantage gap between A14 and N2.

High‑NA EUV stance : TSMC explicitly stated that it will not adopt High‑NA EUV equipment—costing close to $400 million per unit—through 2029. Executives emphasized that continued improvements in conventional EUV, DTCO (Design‑Technology Co‑Optimization), optical shrink, and architectural tweaks are sufficient to sustain scaling without the heavy cost burden.

The overall narrative shows TSMC’s clear industry judgment: AI is the foundational workload, not a fleeting trend, and advanced processes will be supplied on a demand‑driven basis. Mobile chips continue to prioritize stability and cost, while AI/HPC chips chase raw performance, allowing TSMC to maintain its foundry leadership across both markets.