Alibaba’s Qwen3.7‑Max model tops multiple Arena leaderboards, achieves SOTA scores in programming, reasoning, and multilingual benchmarks, runs a 35‑hour autonomous coding task on a custom AI chip with 10× speedup, and demonstrates end‑to‑end desktop app creation and web‑search agents, illustrating a rapid monthly model‑iteration strategy.
Cerebras Systems raised $5.55 billion in the largest 2026 IPO, debuting the wafer‑scale WSE‑3 chip that promises unprecedented inference bandwidth and could erode Nvidia’s dominance, while navigating CFIUS scrutiny, a dramatic financial turnaround, and a shifting AI‑chip market landscape.
The article analyzes Huawei's Ascend AI chip evolution from the 910C baseline through the 950 series' low‑precision FP8/FP4 breakthrough to the 960/970 generation’s 8 PFLOPS performance, highlighting architectural innovations, memory and interconnect upgrades, scenario‑specific models, and a cost advantage over competing solutions.
Huawei’s Ascend 950 series splits a single die into two variants—PR (Prefill & Recommendation) optimized for compute‑intensive inference with low cost, and DT (Decode & Training) tuned for memory‑bandwidth‑heavy generation and training—illustrating a scenario‑driven, P/D‑separated architecture that maximizes efficiency.
At the 2026 North America Technology Forum, TSMC unveiled a complete 2026‑2029 process roadmap, naming the A12 (1.2nm) and A13 (1.3nm) nodes, adding the N2U extension, and announcing that no High‑NA EUV will be required through 2029, signaling a dual‑track strategy for mobile and AI/HPC workloads.
Anthropic suffered seven major Claude outages in half a month, exposing a severe compute shortage that forced the company to announce an early‑stage, $5 billion AI‑chip project, revamp its pricing and subscription model, and confront regulatory KYC hurdles while the broader AI industry pivots away from Nvidia toward custom silicon.
A recent report comparing Alibaba’s home‑grown PPU AI accelerator with NVIDIA’s A800 shows the PPU’s 96 GB HBM2e memory, 700 GB/s bandwidth, PCIe 5.0×15 interface and 400 W power draw surpass the A800 and rival the H20, while large‑scale deployments in China’s telecom sector demonstrate rapidly growing compute capacity.
Huawei’s Ascend 910D AI chip boasts a revamped architecture, 320 TFLOPS half‑precision performance, liquid‑cooling with only 350 W power, and 4 TB/s inter‑chip bandwidth, and the article compares these advantages to previous 910 models, domestic competitors and leading foreign chips such as Nvidia H100, highlighting performance, cost and ecosystem benefits.
The article examines Huawei's Ascend 910D AI processor, highlighting its architectural upgrades, liquid‑cooling power efficiency, and 4 TB/s inter‑chip bandwidth, then compares its performance, cost and ecosystem advantages against domestic rivals such as Cambricon and Kunlun and against foreign powerhouses like NVIDIA H100, AMD MI300 and Google TPU v4.
Huawei is developing a new AI‑focused GPU‑style chip that mirrors Nvidia and AMD architectures, aiming to ease Chinese developers’ shift from Nvidia hardware, but still faces software compatibility hurdles due to reliance on CUDA and ongoing U.S. export restrictions.
Huawei is developing a new AI chip that functions more like a general‑purpose GPU, aiming to match Nvidia and AMD architectures and simplify the transition for Chinese AI developers, while still facing challenges such as adapting CUDA‑based software and overcoming export restrictions.
This article translates and expands on analyst Lennart Heim’s X‑platform report, dissecting Huawei’s newly mass‑produced Ascend 910C AI accelerator, its dual‑chip packaging, performance estimates versus NVIDIA’s H100 and upcoming B200, supply‑chain origins, potential domestic production, and the broader strategic impact on China’s AI competitiveness.
This article provides a concise technical overview of AI chip key metrics—accuracy, throughput, latency, and energy consumption—explains their impact on hardware design, discusses critical design points such as MAC reduction and processing element optimization, and summarizes practical takeaways for evaluating AI accelerator solutions.
This article translates and analyzes Lennart Heim’s deep dive into Huawei’s Ascend 910C AI accelerator, covering its dual‑chip architecture, packaging trade‑offs, performance versus NVIDIA’s H100 and upcoming B200, mysterious supply‑chain origins, and the broader strategic implications for China’s AI competition.
This article provides a detailed technical analysis of Huawei's Ascend 310 AI processor, covering its core compute performance, power efficiency, DaVinci architecture, video/image processing capabilities, recent product roadmap, and the broader industry impact of Huawei's AI chip ecosystem.
This article introduces the basic structure of a general‑purpose CPU used in AI chips, describing the arithmetic‑logic unit (ALU), the different types of registers, and the controller, while also directing readers to extensive AI‑chip technical report collections for deeper study.
This article explains the fundamental performance indicators of AI chips—TOPS, TFLOPS, and precision formats like FP16, FP32, and INT8—while comparing GPU, ASIC, and TPU architectures, highlighting Tensor Core advantages and TPU's superior efficiency over CPUs and GPUs.
The article analyses the historical evolution of Nvidia's NVLink and NVLink C2C interconnect technologies, compares them with PCIe, Ethernet and InfiniBand, and uses these trends to predict future AI‑chip architectures such as the B100 and X100 GPUs, highlighting design trade‑offs and packaging challenges.
Microsoft plans to announce its self‑developed AI processor, codenamed Athena, at the Ignite developer conference in mid‑November, aiming to reduce reliance on Nvidia GPUs and strengthen its AI services such as Azure AI, Bing Chat, and Copilot.
Microsoft plans to launch its first AI‑specific chip, codenamed Athena, at the upcoming Ignite conference, aiming to compete with Nvidia's H100 GPU, reduce reliance on Nvidia, and provide Azure and other cloud customers with a home‑grown AI accelerator for data‑center workloads.
This article provides a comprehensive technical review of Tesla's D1 AI processor and Dojo super‑computer architecture, covering its data‑flow near‑memory design, RISC‑V‑like instruction set, matrix compute units, chiplet packaging, power‑management, cooling solutions, and the associated software compilation ecosystem.
Kunlun Chip’s XPU‑R architecture combines high‑performance SDNN and Cluster compute units, 512 GB/s GDDR6 memory, and PCIe 4.0 interconnect, supported by an LLVM‑based software stack, CUDA‑like programming model, and seamless PaddlePaddle integration, enabling efficient AI training and inference with significant cost and performance gains.
The article reviews Kunlun Chip’s decade‑long development, its self‑designed XPU architecture, key advantages, product generations, performance benchmarks, and diverse industry deployments, illustrating how the company aims to become a globally leading AI computing provider.
The 2022 Beijing Zhiyuan Conference report by Kunlun Core’s chip R&D director outlines AI chip market opportunities and challenges, describes the company’s shift from FPGA clusters to a programmable XPU‑R architecture with 7nm, 256 TOPS INT8 performance, GDDR6 memory and PCIe 4.0, and details current deployments and plans for third‑ and fourth‑generation chips.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
On December 3, Alibaba’s DAMO Academy announced its first AI chip that integrates memory and compute using hybrid‑bond 3D stacking, promising ten‑fold performance gains and 300× energy efficiency for AI workloads such as recommendation systems, and marking a shift from traditional von Neumann designs.
At the 2021 Tencent Digital Ecology Conference, senior executives unveiled three home‑grown chips—ZiXiao for AI inference, CangHai for video transcoding, and XuanLing for high‑performance networking—detailing their 2.5D HBM2e integration, accelerated codecs, and up to four‑fold performance improvements that position Tencent’s custom silicon as a core infrastructure for cloud services.
The article explains why dedicated AI chips (ASICs) are needed, compares their performance and power efficiency to traditional CPUs and GPUs, describes the architecture of Google's TPU and other AI accelerators, and provides historical context for the evolution of AI hardware.
The Cloud Xi conference showcased Alibaba’s breakthrough HanGuang 800 AI chip, delivering performance four times higher than top AI chips, cutting GPU usage by up to 90% in city‑brain video processing and product image recognition, while the Damo Academy celebrated two years of world‑leading research and youth awards.
At the Hangzhou Cloud Expo, Alibaba introduced its first self‑developed AI processor, the Hanguang 800, which delivers up to 78,563 inferences per second on ResNet‑50—four times faster than leading chips—and demonstrates remarkable energy efficiency, powering internal services and upcoming AI cloud offerings.
This week’s tech roundup covers ZTE’s business resumption, the performance‑boosting Git protocol v2, new features in JDK10, Amazon’s lead in global R&D spending, and Facebook’s venture into custom AI chips for video analysis.
