Understanding ARMv8-A Registers: A Guide to SP, LR, PC, CPSR, and More

Overview of ARMv8-A Registers

In ARM processors, registers store data that must be accessed quickly. For operating systems, the most important registers are the Stack Pointer (SP), Link Register (LR), Program Counter (PC), Current Program Status Register (CPSR), and Saved Program Status Register (SPSR). This section focuses on ARMv8‑A.

General‑Purpose Registers

ARMv8‑A provides 31 general‑purpose registers, numbered R0‑R31. In AArch64 state they can be accessed as 64‑bit registers X0‑X30 or as 32‑bit registers W0‑W30.

Stack‑Pointer Registers

Each exception level (EL) has its own stack‑pointer register: SP_EL0 and SP_EL1. If EL2 is implemented, SP_EL2 exists; similarly, SP_EL3 for EL3.

SIMD and Floating‑Point Registers

The SIMD/FPU registers are a set of 32 registers (V0‑V31), each 128 bits wide. They can be accessed in different sizes:

64‑bit double registers D0‑D31

32‑bit single registers S0‑S31

16‑bit half registers H0‑H31

8‑bit byte registers B0‑B31

Program Status Registers

CPSR holds condition‑code flags, interrupt disable bits, the current processor mode, and other control information.

SPSR saves the CPSR state when an exception occurs, allowing the processor to restore the previous state on return. In A64 the processor state is stored in PSTATE , while A32 still uses CPSR. The following diagram shows the SPSR format:

The flag bits N, Z, C, and V have the following meanings:

N : 1 if the result of a signed operation is negative; 0 otherwise.

Z : 1 if the result is zero; 0 otherwise.

C : Set by carry/borrow in addition/subtraction and by the last shifted‑out bit in other operations.

V : Set when signed overflow occurs in addition/subtraction.

Exception Level and SP Selection

The bits M[3:0] in the SPSR determine the exception level and which SP is used:

Link Register (LR, R14)

The LR serves two main purposes:

It stores the return address of subroutines. Instructions like MOV PC, LR or BX LR can be used to return.

During exceptions, the LR of the exception mode holds the address to return to, enabling nested interrupt handling.

Program Counter (PC)

The PC holds the address of the instruction currently being fetched, not the one being executed. With a 4‑byte instruction width, PC points to the address of the current instruction plus 8 bytes.

Processor Modes and Backup Registers

ARMv8‑A defines several execution modes; the same logical register may map to different physical registers depending on the mode. Common modes include:

User (usr) : Normal program execution.

FIQ : Fast interrupt for high‑speed data transfer.

IRQ : Standard interrupt handling.

Supervisor (svc) : Privileged mode for the operating system.

Abort (abt) : Entered on data or instruction fetch aborts.

Undefined (und) : Entered on execution of undefined instructions.

System (sys) : Privileged mode for OS tasks.

Additional modes such as Monitor (mon) for secure/non‑secure state switching and Hypervisor (hyp) for virtualization support are also defined.

Conclusion

This section introduced the most commonly used ARMv8‑A registers in operating systems and highlighted their relationship with exception levels. The next article will explore ARMv8‑A exception levels in detail.