Understanding x86 Interrupts: Vectors, Descriptors, and Handling Mechanisms

Interrupt Vectors and Descriptors

Interrupt vectors are used in real‑mode; the processor combines a segment address and an offset to locate the interrupt handler. In protected mode, interrupt descriptors serve the same purpose but include additional fields, making them more complex and powerful.

Classification of Interrupts

Internal Interrupts

Generated inside the CPU, such as division‑by‑zero (IRQ 0) or illegal instruction (IRQ 6). These are also called exceptions. Software interrupts (e.g., int3) are triggered by the int instruction and are useful for debugging.

External Interrupts

External signals arrive on the CPU’s INT (non‑maskable) and INTR (maskable) pins. The classic 8259A Programmable Interrupt Controller (PIC) provides 8 IRQ lines per chip; cascading two chips yields 15 usable interrupt inputs for devices such as keyboard, mouse, serial ports, and disks.

The master PIC’s INT output connects to the CPU’s INTR pin. The slave PIC’s INT output connects to the master’s IRQ 2 line.

Each 8259A chip can be programmed via its registers to map IRQ lines to specific interrupt numbers.

Interrupt Numbers

The x86 CPU supports 256 interrupt numbers (0‑255). Numbers 0‑31 are reserved for exceptions and non‑maskable interrupts; the rest are used for external hardware interrupts. For example, IRQ 0 (system timer) is assigned number 32, and Linux system calls use number 128.

When using the 8259A, IRQ 0 is typically mapped to interrupt number 32, and subsequent IRQs receive consecutive numbers.

Interrupt Vectors and Service Routines

When an interrupt occurs, the CPU reads the interrupt number, looks up the corresponding entry in the interrupt vector table (or descriptor table in protected mode), and jumps to the Interrupt Service Routine (ISR).

In real‑mode, a vector entry consists of a 4‑byte record: a 2‑byte segment address followed by a 2‑byte offset. The physical address of the handler is calculated as (segment << 4) + offset. For example, interrupt 2 might point to segment 0x1000, offset 0x2000, yielding a physical address of 0x12000.

Linux runs in protected mode, so it uses interrupt descriptors instead of raw vectors. Each descriptor stores a segment selector and an offset, serving the same lookup purpose.

Installing an Interrupt Handler

Write a normal function in code. Place the function’s machine code at a chosen memory location. Set the segment:offset pair (or descriptor) for that location in the interrupt table.

BIOS, the operating system, and hardware often provide default handlers for common interrupts.

Saving and Restoring CPU Context

Before transferring control to an ISR, the CPU automatically pushes registers such as CS, IP, FLAGS, and others onto the stack. After the ISR finishes, the CPU pops these values to resume the interrupted program.

Summary: The Essence of Interrupts

Provide a mechanism for asynchronous execution. Offer a gateway for user programs to enter kernel code.

Interrupts introduce an indirection layer: a fixed‑location table holds pointers to handlers that can reside anywhere in memory, enabling flexible and decoupled system design.