The article explains that a CPU continuously repeats four stages—fetch, decode, execute, and write‑back—while highlighting the role of registers, the differences between CISC and RISC instruction sets, how function calls build and tear down stack frames, and why user‑mode coroutines are far lighter than kernel threads.
The article compares Huawei’s Kunpeng ARM‑based processors with the Haiguang x86 line, detailing their architectural designs, ecosystem support, autonomy progress, and recommending specific deployment scenarios where each platform’s strengths—such as energy efficiency, software compatibility, or low‑migration risk—are most advantageous.
This article traces the quirky lineage of Intel’s numbered processors from the 4004 to the Pentium era, explains why the 32‑bit architecture is called x86, covers AMD’s x86_64 extension, Microsoft’s Windows naming, and clears common misconceptions about bit‑width naming.
The article humorously traces Intel’s processor lineage from the 1971 4004 to modern x86_64, explaining why 32‑bit systems are called x86, how naming conventions evolved, the role of AMD’s extensions, Microsoft’s Windows naming, and the quirks of folder naming, while debunking common misconceptions about bit‑width and architecture.
This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.
This report provides a comprehensive technical analysis of Zhaoxin’s x86 processor lineup—from early ZX‑C chips to the latest KX‑7000 desktop/embedded series and KH‑40000 server CPUs—detailing architecture, process technology, performance specs, security features, and real‑world deployments across government, education, and enterprise sectors.
This article explains how modern multiprocessor hardware and compiler optimizations affect program behavior, introduces memory consistency models such as sequential consistency, x86‑TSO, and ARM/POWER weak models, demonstrates their differences with litmus tests, and discusses the DRF‑SC guarantee for data‑race‑free programs.
This article traces Intel's processor lineage from the 1971 4004 to modern x86_64 CPUs, explains why the 32‑bit operating system is called x86 despite varying bit widths, and clarifies the naming conventions used by AMD and Microsoft for 64‑bit platforms.
The 2025 China Xinchuang server vendor research report shows procurement rising from 458.2 billion yuan in 2023 to 505.8 billion yuan in 2024 (10.4% growth), highlights regional gaps, sector shares, CPU architecture shifts, vendor competition, and predicts a move toward high‑performance, intelligent, and green servers by 2027.
The 2024 Chinese server market grew to 505.8 billion yuan, up 10.4% from 2023, with Beijing leading procurement, a shift toward higher‑core CPUs, dominant x86 architecture, rising ARM presence, and emerging trends toward high‑performance, intelligent, green, and ecosystem‑driven servers.
This article analyses China's 2024‑2026 information‑technology innovation (信创) hardware market, forecasting a 7.9‑trillion‑yuan size, examining CPU instruction‑set trends, licensing models, and the strategies of six domestic CPU vendors, while comparing their ecosystem compatibility and market prospects.
The article analyzes China’s Xinchuang hardware sector, forecasting a market size of 7.89 trillion yuan by 2026, examining shifts toward high‑performance domestic CPUs, comparing CISC (x86) and RISC (ARM, LoongArch, SW_64) instruction sets, and evaluating the strengths, licensing models, and ecosystem challenges of six major Chinese CPU manufacturers.
This guide provides a thorough introduction to x86 assembly language, covering GNU syntax, CPU architecture, registers, instruction formats, data types, memory models, and practical examples with NASM and GNU as, enabling readers to write efficient low‑level code and deepen their understanding of computer systems.
This article explains why mastering assembly language is crucial for understanding how computers execute code, covering the nature of low‑level languages, CPU instruction encoding, registers, memory models such as heap and stack, and walks through a complete x86 example with detailed instruction analysis.
This article compares the major instruction set architectures—x86, ARM, and RISC‑V—explaining their CISC versus RISC philosophies, historical evolution, technical trade‑offs, and the current market landscape of domestic and global CPU vendors.
This article provides a comprehensive overview of servers, explaining what they are, their logical and hardware composition, firmware and operating systems, various classification schemes, and the ongoing competition between X86 and ARM architectures in modern data centers.
This article provides a comprehensive overview of servers, explaining what they are, their hardware components, classification by form factor, instruction set and processor count, and examines the market dynamics of X86 versus ARM architectures, supported by recent industry data and cost analyses.
The article explains the evolution from segment to paging addressing, details Linux’s multi‑level page‑table structures for x86 and ARM, walks through key macros and assembly routines, and provides a complete kernel module example that translates a virtual address to its physical counterpart.
This article traces the evolution from real‑mode segmentation to modern paging, explains segment and page‑table structures on x86 and ARM, dissects kernel macros such as PGDIR_SHIFT and PUD_SHIFT, and demonstrates a kernel module that translates a process's virtual address to its physical address.
The 2024 Chinese server CPU industry overview reveals a rapid market expansion driven by data‑center growth and the Xinchuang initiative, outlines the dominance of X86 and ARM ecosystems, details recent market size and forecast figures, and analyzes competitive strengths, ecosystem maturity, and instruction‑set autonomy among domestic vendors.
This comprehensive guide walks IT and DevOps professionals through understanding ARM and x86 architectures, setting up the build environment, creating and customizing base images, optimizing size and performance, and packaging for distribution, with practical commands and best‑practice recommendations.
This article introduces x86 assembly language, explaining its historical origins, the role of CPU registers such as EAX and ESP, the heap and downward‑growing stack memory models, and demonstrates basic stack‑frame operations like push, call, mov, add, pop, and ret through a simple compiled example.
This article explains how PRTOS implements a separated kernel architecture with paravirtualization, details the hardware‑dependency layer, outlines the constraints of embedded virtualization, and walks through CPU frequency calibration and interrupt‑vector initialization for x86‑based embedded hypervisors.
The report analyzes the accelerating shift from x86 to ARM in AI‑enabled devices, covering architectural differences, market share dynamics, Apple’s successful ARM transition, Microsoft’s ARM ecosystem, Intel’s heterogeneous AI processors, rising memory demands, and future industry forecasts for 2024‑2027.
The 2024 China server CPU industry overview analyzes the dominance of X86 and ARM ecosystems, presents market size growth from 2018 to 2028, examines competitive advantages of domestic vendors, and discusses policy-driven demand and pricing challenges shaping the domestic CPU market.
The article investigates undocumented x86 opcodes, describing a depth‑first search that uses page‑faults to locate hidden instruction boundaries, and reports finding dozens of executable but undocumented instructions on Intel and AMD CPUs, highlighting potential security risks and the need for vigilant hardware analysis.
This article provides a comprehensive overview of contemporary processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their design philosophies, historical evolution, advantages, disadvantages, and the current landscape of domestic and international CPU development.
The article analyzes the shift from x86 to ARM in server hardware, compares CISC and RISC instruction sets, reviews domestic Chinese CPU projects, examines GPU/NPU/FPGA accelerators, and proposes concrete ARM instruction‑set, compiler, and operating‑system standards for the telecom industry.
This article presents a detailed performance comparison of cloud RDS MySQL services across major providers, examining x86 versus ARM architectures, various storage options, and cost‑performance ratios, and concludes with practical recommendations for choosing the most suitable configuration.
This article provides a comprehensive overview of modern processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their historical development, design philosophies, advantages, disadvantages, and current market adoption in both domestic and global contexts.
The article analyzes the evolution of cloud computing and the challenges of migrating applications from X86 to ARM architectures, covering cross‑architecture adaptation, virtualization, containerization, cloud‑native practices, language‑specific impacts, and a real‑world case study of the BlueMail platform.
Although both ARM and x86 processors aim to balance transistor count, program complexity, speed, power consumption, and cost, their fundamentally different architectures—RISC versus CISC—make them non‑interchangeable, leading to distinct trade‑offs in performance, energy efficiency, and application suitability across devices from smartphones to supercomputers.
The article explains the fundamental differences between ARM and x86 CPUs, compares RISC and CISC instruction set philosophies, discusses how each architecture balances transistor count, performance, power consumption and cost, and highlights why ARM dominates low‑power devices while x86 remains prevalent in high‑performance computers.
This article examines the fundamental differences between CISC (x86) and RISC CPU architectures, compares global market shares of Intel, AMD, and domestic Chinese processors, and evaluates the performance, ecosystem, and security advantages of leading CPUs such as HaiGuang in various computing scenarios.
The article reflects on how programming has become increasingly abstract, causing developers to overlook the CPU, memory, and low‑level architecture, and argues that revisiting these fundamentals is essential for deeper technical competence in today's software industry.
The article explains how modern CPUs reorder instructions at compile‑time and runtime, the role of store buffers and invalid queues, why memory barriers are needed for visibility across cores, and compares sequential consistency guarantees on x86 versus ARM/Power architectures.
This article examines China’s domestic CPU market, profiling six manufacturers, comparing their architectures (ARM, x86, LoongArch, RISC‑V, Alpha), detailing technical specifications, performance benchmarks, ecosystem support, and the impact of national programs on their development.
This article compares the dominant X86 and ARM CPU architectures, explaining their performance versus power trade‑offs, CISC versus RISC designs, typical application domains, and the recent surge of ARM‑based servers driven by cloud, HPC and edge computing demands.
This article provides a comprehensive overview of China's leading domestic CPU vendors—including HaiGuang, Kunpeng, Loongson, Shenwei, Feiteng, and Zhaoxin—detailing their architectures, performance characteristics, market positioning, and the national initiatives that support their development.
The article provides a comprehensive overview of the role of CPUs and GPGPUs in modern server architectures and AI workloads, discussing hardware fundamentals, instruction set architectures, market trends, and the emerging importance of heterogeneous computing for high‑performance and energy‑efficient processing.
This article summarizes the 2022 Chinese server CPU research framework, covering server fundamentals, logical architecture, CPU roles and cost impact, instruction-set classifications (CISC vs RISC), major architectures (x86, ARM, MIPS), the industry value chain, market size trends, and global competitive dynamics across server, desktop, and mobile segments.
This article explains which instruction sets support atomic operations, detailing the principles behind x86’s LOCK prefix and ARM’s exclusive load/store mechanisms, illustrating how single‑processor and SMP systems handle atomicity, and showing Linux kernel implementations for atomic increment and compare‑and‑swap.
This article explores whether modern CPUs contain undocumented or hidden instructions, explains the challenges of searching the variable‑length x86 ISA, presents a depth‑first algorithm that skips irrelevant bytes, shows how to infer instruction length using page‑fault side‑effects, and reveals discovered hidden opcodes on Intel and AMD processors.
This article provides a comprehensive guide to Linux memory management on x86 32‑bit systems, covering virtual and physical address spaces, kernel zones, user‑space regions, key data structures, and practical commands for inspecting memory layout.
This article explains x86 assembly direct and indirect memory addressing, the meaning of address length, how to use registers like BX for indexed access, and demonstrates loop‑based multiplication with detailed code examples and execution analysis.
The article investigates whether modern x86 CPUs contain undocumented or hidden instructions, explains how to search the instruction space using a depth‑first algorithm that leverages page‑fault side‑effects to determine instruction length, and presents the results of uncovering such hidden opcodes on Intel and AMD processors, highlighting the potential security risks.
This article provides a comprehensive overview of servers, covering their definition, logical and hardware architecture, firmware and operating systems, various classification schemes, and a detailed comparison of X86 and ARM server platforms in the context of modern cloud computing.
This article explains how Tencent's RegionEIP combines X86‑based load distributors and P4 programmable switches to deliver high‑performance, highly available public network access for cloud services, detailing zone disaster recovery, traffic‑shaping algorithms, four‑level routing priority and port‑redundancy designs.
An extensive analysis traces the evolution of CPU architectures—from early Intel 4004 to modern x86, ARM, RISC‑V and MIPS—examining their technical differences, market shares, recent performance gains, and the shifting competitive landscape across servers, desktops, mobile devices, and emerging IoT applications.
Servers, the high‑performance backbone of cloud and data‑center infrastructures, differ from ordinary PCs in stability, hardware, and firmware; they come in various logical and physical forms, are classified by architecture, CPU count, and application, and the market now sees a competitive split between X86 and ARM designs.
The article analyzes the current X86 market dominance of Intel, AMD's rapid advancement with its Zen architecture and 7nm process, the competitive landscape of server and consumer CPUs, and the emergence of Chinese domestic processors built on licensed X86 technology.
This article provides a comprehensive analysis of CPU architecture evolution, workflow, historical milestones, CISC versus RISC competition, the emergence of RISC‑V, China's domestic processor initiatives, and current market share trends across servers, desktops, and mobile devices.
The article analyzes the current X86 market, comparing Intel’s dominance with AMD’s rapid Zen‑based advancements, outlines AMD’s CPU roadmap and EPYC server releases, and examines how Chinese manufacturers are leveraging licensed Zen designs to build domestic X86 processors.
This article explains the fundamentals of x86 interrupt handling, covering the distinction between interrupt vectors and descriptors, classification of internal and external interrupts, the role of the 8259A PIC, how interrupt numbers are assigned, and the mechanisms for saving and restoring CPU state during an interrupt.
This article provides a comprehensive introduction to the fundamentals of x86 Linux, covering the historic Intel 8086 processor, segment descriptors, main memory organization, registers, bus architecture, CPU addressing modes, control mechanisms, and the basic instruction execution cycle.
The article analyzes the current X86 market dominance of Intel, AMD's growing share and Zen CPU roadmap, details AMD's strategic spin‑offs and fabless collaborations, and examines how Chinese companies are leveraging Zen architecture for domestic processor development.
This article provides a comprehensive analysis of the BIOS and BMC firmware ecosystem, covering technical fundamentals, the value chain from CPU to end devices, market size estimates, major global and Chinese vendors, and the risks and investment opportunities shaping the industry.
This article provides a comprehensive overview of servers, covering their definition, hardware and firmware composition, various classification schemes (form factor, instruction set, processor count, application type), and the ongoing market competition between X86 and ARM architectures.
This comprehensive guide explores the myriad x86/x64 CPU registers—including general, flag, instruction, segment, control, debug, descriptor, task, and model‑specific registers—explaining their roles, how they interact in memory addressing, multitasking, system calls, and debugging, while highlighting key differences between 32‑bit and 64‑bit modes.
This article chronicles the evolution of running macOS on non‑Apple hardware—from the early PowerPC‑based “black Apple” experiments, through Intel transitions, legal battles, and the development of bootloaders like Chameleon, Clover, and OpenCore—highlighting technical challenges and milestones.
The article reviews the historical shift from mainframes to x86, highlights the emerging limitations of x86 in the era of mobile and cloud workloads, and details how Huawei's ARM‑based Kunpeng platform and its migration toolchain enable efficient cross‑architecture software migration and performance optimization.
This article surveys the development of server hardware, comparing CISC‑based x86 CPUs that currently dominate the market with emerging ARM‑based RISC designs, and examines how Chinese domestic processors and cloud providers are reshaping the server ecosystem through performance, power efficiency and licensing strategies.
With the rise of mobile, IoT, and edge computing, the long‑standing dominance of x86 is challenged, prompting developers to migrate applications to ARM‑based Kunpeng platforms; this article explains the architectural differences, a five‑step migration methodology, and detailed C/C++ compilation considerations including instruction, macro, and SIMD adaptations.
This article explains what a server is, its logical and hardware architecture, the role of firmware and operating systems, various classification methods—including form factor, instruction set, processor count and application type—and compares the market dynamics and technical advantages of X86 and ARM servers.
The article examines the historical shift from mainframes to x86, highlights the emerging need for ARM-based solutions like Huawei's Kunpeng processors, and provides detailed migration strategies, tools, and best‑practice steps for moving C/C++ and other workloads from x86 to ARM architectures.
This article explains the principles and challenges of migrating software from x86 to Huawei's Kunpeng ARM64 platform, covering instruction‑set differences, dependency analysis, compilation adjustments, performance testing, and the suite of tools Huawei provides to streamline the migration process.
This article explains the fundamental differences between CISC and RISC processor designs, outlines their respective advantages and drawbacks, and compares three major CPU architectures—x86, ARM, and MIPS—highlighting their histories, features, and typical application domains.
The article provides a detailed comparison between ARM's RISC-based processors and Intel's x86 CISC architecture, covering design philosophy, performance, power consumption, expansion capabilities, operating system compatibility, software development tools, and cost considerations for various terminal applications.
This article provides a comprehensive overview of the origins, market evolution, and technical characteristics of PowerPC, x86, and ARM processors, comparing their performance, power consumption, vector capabilities, and ecosystem support while highlighting why each architecture succeeded or struggled in the industry.
QNAT is a high‑performance, open‑source x86 NAT solution developed by 360 OPS, featuring flexible address‑pool selection, session limits, traffic pass‑through, detailed session logging, and a CLI management interface, and is deployed in many IDC and office network egress points.
This article provides a detailed comparison between ARM's RISC-based processors and Intel's CISC‑based x86 CPUs, covering design philosophies, performance, power consumption, expansion capabilities, operating‑system compatibility, software development tools, cost factors, and suitable application scenarios.
This article examines why converting a double value that exceeds the long range yields opposite signs on x86 and ARM processors, explains the underlying CPU instruction differences, presents detailed conversion tables, and reviews essential floating‑point and two's‑complement integer concepts.
This article chronicles the development of the x86 and ARM ecosystems, detailing early competitors, strategic alliances, technological shifts, market battles, and future trends that have shaped the semiconductor industry and the broader computing landscape.
This article explains how the V8 JavaScript engine generates machine code for floating‑point addition on Intel x64, covering V8’s architecture, the IEEE‑754 representation that causes precision loss, and a step‑by‑step analysis of the relevant C++ source and the resulting addsd instruction.
This article provides a comprehensive, illustrated guide to the entire manufacturing workflow of an Intel Core i7 CPU—from raw silicon extraction and purification, through photolithography, doping, and multilayer metal deposition, to testing, packaging, and future architectural outlooks including x86 limitations and the rise of RISC‑V and the RIOS lab.
This article provides a comprehensive overview of RISC architecture and its major implementations—including ARM, x86/Atom, MIPS, and PowerPC—detailing their design principles, performance characteristics, market adoption, and relevance to embedded and mobile systems.
This article chronicles the development, competition, and strategic shifts of the x86 and ARM processor ecosystems from their early days through recent innovations, highlighting key architectural decisions, market dynamics, and the evolving role of software abstraction layers in shaping the semiconductor landscape.
This article explains the principles of Reduced Instruction Set Computing (RISC), compares its performance advantages over Complex Instruction Set Computing (CISC), and surveys major RISC families such as ARM, MIPS, PowerPC, as well as Intel's low‑power Atom line and their roles in modern devices.
Arm announced its upcoming Neoverse N1 platform and E1 CPU, sparking a heated debate with Linus Torvalds over ARM versus x86 server dominance, while developers like antirez argue for ARM's growing viability in server and cross‑development scenarios.
The article offers a comprehensive, historically grounded analysis of the x86 and ARM ecosystems, tracing their origins, competitive battles, technical innovations, market shifts, and future challenges while highlighting why software ecosystems, licensing models, and emerging technologies shape CPU dominance.
This article introduces the fundamentals of x86 assembly language, explaining why low‑level code is needed, the history of assembly, CPU registers, the heap and stack memory models, and walks through a complete example with detailed explanations of each assembly instruction.
The article explains how Alibaba tackled the slowdown of Moore's law and TCO constraints by progressively customizing X86 CPUs—from selecting vendor SKUs to requesting bespoke specifications and adding micro‑code features—to boost performance and efficiency for massive events like Double 11.
This article explores x86 performance optimization by comparing a simple sum‑of‑array loop with and without a pre‑sort step, demonstrating how branch prediction and cache behavior can make seemingly redundant code run up to three times faster, and outlines practical benchmarking principles and common pitfalls.
This article reviews the 2016 Dyn DDoS incident, explains why DDoS attacks remain a critical security challenge, and details Alibaba's internally built high‑performance DDoS mitigation solution AliGuard, covering its development timeline, multi‑user architecture, scalability from 40 Gbps to over 400 Gbps, and deployment models.
The article traces the evolution of minicomputers from IBM's RISC‑based Power series and proprietary UNIX systems through a competitive era of closed architectures, to the modern shift toward open X86‑based platforms, highlighting how open standards, Linux and Intel’s strategies reshaped the market and reduced customer risk.
The article reviews the historical development from closed‑architecture mainframes to open X86‑based small servers, analyzes Huawei's Kunlun and competing products, and discusses their RAS features, partitioning technologies, and suitability for high‑availability financial database workloads.
