Unlocking DDR Memory: From Basics to Advanced Architecture

Memory is a frequently encountered hardware component in embedded systems, yet many engineers only configure parameters supplied by chip vendors without understanding the underlying principles.

1. Scenario

Developer Xiao Zhang bought two DDR3 modules to upgrade a laptop to 8 GB, but the specifications on the packaging (2Rx8, PC3‑10600S, 1333 MHz) were confusing, prompting a deeper dive into DDR details.

2. DDR History and Concepts

2.1 ROM and RAM

RAM is readable, writable, and fast, while ROM is read‑only and retains data without power. RAM can be SRAM (static) or DRAM (dynamic).

2.2 Development Timeline

Memory capacity grew from kilobytes to gigabytes, moving from DIP chips on early PCs to SIMM modules, then to DIMM modules as CPU data‑bus widths increased.

EDO DRAM (early 1990s) offered larger capacity and higher speed for 486 and early Pentium CPUs.

SDR SDRAM introduced synchronous operation with the CPU clock, improving data transfer efficiency.

DDR generations: DDR, DDR2, DDR3, DDR4, and now DDR5, each increasing data rate, reducing voltage, and expanding capacity.

Key specifications:

DDR: Double Data Rate, transfers data on both clock edges (e.g., DDR‑266 vs. PC133 SDRAM).

DDR2: 1.8 V, 240‑bit interface, higher prefetch (4 n).

DDR3: 1.5 V, 240‑bit interface, 8 n prefetch, common in modern PCs.

DDR4: 1.2 V, 16‑bit prefetch, bank groups, up to 3200 MT/s.

2.3 DDR Variants

DIMM types include RDIMM (registered, server‑grade, often ECC), UDIMM (unbuffered, typical desktop), SO‑DIMM (laptop), and Mini‑DIMM (blade servers).

Labeling conventions such as DDRx‑yyy (data rate) and PCx‑zzzz (bandwidth) help identify speed and generation.

2.4 Detailed DDR Differences

Advancements from DDR to DDR5 involve lower operating voltage, larger chip capacity, higher I/O rates, and architectural changes like increased bank count, bank groups, larger prefetch (2 n → 4 n → 8 n), and burst length adjustments.

3. Memory Principles

The physical hierarchy is: Channel > DIMM > Rank > Chip > Bank > Row/Column.

Example: a dual‑channel i7 CPU can host two DIMMs per channel; each DIMM may contain two ranks, each rank comprising eight chips. With a 64‑bit data bus, eight 8‑bit chips form one rank.

Each bank is a two‑dimensional array of rows and columns; a memory cell stores a byte. Address lines are multiplexed to first select a row, then a column, effectively expanding addressable space.

Address‑line allocation example: 20 address lines and 16 data lines can theoretically address 2 MB, but actual DDR designs use time‑multiplexing and bank groups to reach capacities of 1 GB per chip.

Bank groups in DDR4 allow additional interleaving without changing prefetch, boosting I/O speed while keeping the 64‑bit data lane.

4. Summary

The chapter reviewed DDR evolution and internal architecture, emphasizing the hierarchy (Channel → DIMM → Rank → Chip → Bank → Row/Column) and the role of address, control, clock, and data signals in modern DDR4 modules.

5. References

"The Story of Memory" – Rambus battle (zhihu.com/p/69420038)

DRAM history overview (sohu.com/a/331550672_100246125)

Deep dive into hardware principles (zhihu.com/p/26327347)

LPDDR4 specification (csdn.net/YJFeiii/article/details/105469366)