WAIC 2026: Dissecting Five Supernode Architectures and Their Trade‑offs

WAIC 2026’s AI compute exhibition marked a shift from single‑chip displays to rack‑scale "supernode" solutions, with vendors prominently featuring the term on their booths and listing impressive card counts (1024, 640, 128, etc.).

The article explains that traditional AI clusters use a two‑stage communication model: high‑bandwidth, low‑latency links inside a server, and slower InfiniBand or RoCE networks between servers. Large‑scale models (tensor‑parallel, MoE, long‑context inference) expose the bandwidth and latency bottlenecks of this architecture, causing compute units to idle.

Supernode concepts aim to extend the high‑bandwidth domain from a single server to an entire rack, multiple racks, or larger logical systems. Dedicated switch chips and high‑speed protocols connect accelerators, while the software stack provides topology awareness, task scheduling and fault recovery.

Huawei demonstrated a 1024‑card Atlas 950 SuperPod with 1 EFLOPS FP8 performance, 256 TB unified address space, TB‑level interconnect bandwidth and 3 µs round‑trip latency. Its core is the UB 2.0 interconnect protocol (Lingqu), which unifies NPU, CPU, memory and switch addressing. Huawei’s white‑paper claims UBMesh achieves >95 % linear scaling and a cost‑efficiency 2.04× that of traditional Clos networks. However, the unified address space does not guarantee uniform access latency; software must be topology‑aware to avoid hidden NUMA costs. Huawei’s roadmap targets 8192 cards by 2025, while the WAIC demo remains at 1024 cards.

ZTE tackled the physical layer first. Its Orthogonal Electrical eXchange (OEX) removes intra‑rack copper cables by inserting compute and switch trays orthogonally, shortening SerDes links by >30 % and cutting insertion loss by ~6.5 dB. The design supports 128‑card dense cabinets and reduces maintenance from hours to minutes. After cabinet assembly, ZTE adds a distributed dOCS optical switch that dynamically reconfigures optical paths, enabling more direct inter‑cabinet connections and reducing multi‑stage electrical switching. The OEX+dOCS solution won the WAIC SAIL award, but the open‑ecosystem claim brings challenges: heterogeneous chip operators, differing operator libraries, numeric formats and compilation tools require per‑stack validation.

Sugon promotes its scaleX640, which it defines as "up to 640 accelerator cards per cabinet" (two cabinets form a 1280‑card unit). High density is achieved through dense blades, orthogonal structures, high‑voltage DC power and immersion phase‑change liquid cooling, yielding a PUE of 1.04. Beyond the cabinet, Sugon uses scaleFabric 400 Gbps native RDMA to interconnect 16 scaleX640 cabinets into a 10 240‑card cluster. The approach offers physical openness and multi‑vendor support, yet public data on per‑card effective bandwidth, latency curves, and whether all 640 cards share identical communication semantics remain unavailable.

H3C (新华三) offers the UniPoD S80000 product family, which scales from 32 to 1024 cards per unit and can expand to 16 384 cards. It employs a Scale‑Up switch with a 102.4 Tbps chip and supports both NPO and CPO optical interconnect forms. The architecture bundles compute, storage, cloud platform, security and operations into a single product line, with the upper‑layer control plane handling topology awareness, logical slicing, fault recovery and multi‑tenant isolation. While integration is valuable for enterprise AI platforms, the flexibility leads to large performance variance across configurations, as different card counts, accelerators, interconnect protocols and optics affect real‑world results.

Alibaba follows a closed‑loop from silicon to cloud. It designed the M890 AI chip (144 GB memory, 800 GB/s inter‑chip bandwidth) and the Pangu AL128 cabinet that packs 128 M890 chips, delivering PB/s‑level intra‑cabinet bandwidth. The solution is already deployed on Alibaba Cloud’s Bailei platform, supporting models such as Qwen, DeepSeek and Kimi. Alibaba also open‑sourced the T‑Head SAIL software stack covering OS, SDK and interface layers. The advantage lies in workload‑driven optimization—real cloud workloads expose bottlenecks that feed back into chip, interconnect and scheduler design. However, this optimization primarily serves Alibaba’s own cloud and ecosystem; external developers may face migration hurdles due to compiler, operator‑library and debugging‑tool coverage.

The article concludes that the five routes place different engineering priorities—interconnect protocol, cabinet structure, liquid‑cool density, full‑stack ops, and cloud‑hardware co‑design—under the common name "supernode". Future competition will no longer be judged by raw card counts but by metrics such as effective all‑to‑all bandwidth for MoE models, tail latency, sustained compute time per month, fault‑isolation granularity, and token‑per‑watt efficiency. The next step is to evaluate how large a high‑bandwidth boundary each vendor defines, whether software can reliably utilise resources within that boundary, and what costs arise when operating beyond it.