What’s Next in 3D Chip Packaging? Inside TSMC’s SoIC, InFO, and CoWoS Advances

At Hot Chips 33, leading semiconductor companies such as Intel, AMD, IBM, ARM, NVIDIA, Samsung, and Qualcomm, along with startups like Skydio, EdgeQ, and Esperanto, presented detailed analyses of their newest chip technologies.

TSMC’s 3D Fabric Roadmap

TSMC showcased its most advanced 3D packaging platforms, including SoIC, InFO, and CoWoS, and released a roadmap for CoWoS technology. The company demonstrated next‑generation solutions for small‑chip architectures and memory designs, featuring advanced thermal treatment and COUPE heterogeneous integration.

InFO (Integrated Fan‑Out)

InFO utilizes a reconstituted wafer formed by face‑down embedded molds, surrounded by a molding compound. Redistribution layers (RDL) are fabricated on an epoxy wafer, and the InFO‑L variant embeds silicon “bridge” dies between molds to improve inter‑die connectivity.

CoWoS (Chip‑on‑Wafer‑on‑Substrate)

2.5D CoWoS employs micro‑bump connections to integrate chips and high‑bandwidth memory stacks on a silicon interposer. The original CoWoS products used a silicon interposer and silicon‑based lithography for RDL manufacturing, with TSVs providing connections to package bumps, enabling high interconnect density for HBM interfaces.

SoIC (Stack‑on‑Integrated‑Circuit)

SoIC offers hybrid bonding for vertical integration between modules. Molds can be bonded face‑to‑face, and TSVs in thinned molds provide connectivity. Recent SoIC test chips (configuration N5 CPU die with N6 SRAM die) demonstrated vertical stacking of a CPU’s last‑level cache, with a commercial product expected in Q1 2022.

SoIC Design Flow

The advanced design flow for vertical mold integration includes top‑down system partitioning into individual dies and early thermal analysis of the composite configuration. Early thermal analysis identifies low‑thermal‑resistance paths (the “chimney” effect) and refines hotspot regions with finer mesh grids.

Thermal‑Aware Timing Derating

TSMC integrates thermal analysis results into static timing analysis by applying derating factors based on temperature gradients. Typical path temperature gradients are ~5‑10 °C, while larger gradients of ~20‑30 °C are considered feasible for SoIC paths.

Testing Standards

SoIC testing aligns with IEEE 1838, which defines module‑to‑module interface tests similar to IEEE 1149 boundary‑scan for PCB‑level testing. While sufficient for low‑speed I/O, high‑speed interfaces require broader BIST methodologies.

LiteIO IP

TSMC provides a “LiteIO” design for die‑to‑die connections, optimizing layout to reduce parasitic ESD and antenna capacitance, thereby achieving higher data rates between bare dies.

EDA Enablement

Major EDA vendors have collaborated with TSMC to develop tool features that support InFO and SoIC packaging, enabling designers to model, simulate, and verify advanced 3D integration workflows.

Conclusion

TSMC continues to invest heavily in 2.5D/3D advanced packaging, with recent initiatives focusing on direct chip‑attach SoIC methods—covering partitioning, physical design, and analysis. Early thermal analysis remains a critical step, and the company’s SoIC eTV qualification test results indicate rapid growth, with 2022 expected to witness a surge in SoIC designs.