Why CPUs Need Interrupts: From PIC to APIC and Affinity Explained

Interrupt Mechanism

The CPU is described as a workshop where the core constantly executes instructions but must also communicate with peripheral units such as the keyboard, mouse, disk and network card. When a peripheral needs service it sends an interrupt signal, causing the CPU to pause the current instruction stream, save the execution context on the stack, and jump to an interrupt‑handling routine.

To control whether an interrupt can pre‑empt the current work, the eflags register holds a mask bit: when the bit is 1 the CPU accepts interrupts; when it is 0 the CPU ignores them. Some interrupts, like the non‑maskable interrupt ( NMI), cannot be disabled because they indicate critical events such as power loss or severe hardware errors.

8259A PIC

Because many devices may request service, the system uses a programmable interrupt controller (PIC), historically the 8259A. Each device is assigned an interrupt vector number, and the PIC maps that vector to an entry in the Interrupt Descriptor Table ( IDT), which stores the address of the corresponding handler routine. The IDT contains 256 entries and is located in memory; the idtr register points to its base address.

Exceptions (e.g., division‑by‑zero or page faults) are also dispatched via the same IDT, making exception handling synchronous while interrupts are asynchronous.

APIC

When systems grew to multiple cores, the 8259A could not scale. It was replaced by the Advanced Programmable Interrupt Controller (APIC). APIC consists of two parts: the I/O APIC, which receives external interrupt signals and distributes them, and the Local APIC, which resides in each core (or "CPU workshop") and handles the actual delivery.

The I/O APIC forwards interrupts to the appropriate Local APICs, enabling up to eight cores to process requests in parallel. It also supports Inter‑Processor Interrupts ( IPI) that allow one core to interrupt another.

Interrupt Affinity

During a network traffic surge, the single‑core model caused one core to be overwhelmed. The discussion introduces interrupt affinity : the ability to bind specific interrupt vectors to particular cores. The operating system exposes a configurable mask via the smp_affinity interface, allowing administrators to steer interrupts to less‑loaded CPUs.

This concept mirrors CPU affinity for threads, where a thread can request to run on a specific core to preserve cache locality and improve performance for cache‑intensive workloads.