Why Do x86 and ARM Convert Double‑to‑Long Differently? Explore the CPU Secrets

Problem Phenomenon

A customer discovered that converting a double value that exceeds the range of a long back to long yields different signs on x86 (<0) and arm64 (>0). Example code: aa * (double)10 stored in a double temporary then assigned to long bb.

Problem Analysis

0x7FFFFFFFFFFFFFFF is the maximum positive value a signed 64‑bit long can represent. Multiplying it by 10 exceeds the long range. The expression is evaluated in a double temporary (ARM uses d‑series registers, x86 uses xmm 128‑bit registers). When the out‑of‑range double is cast back to long, the conversion behavior differs between Kunpeng (ARM) and x86.

On ARM the conversion instruction is fcvtzs; on x86 it is cvttsd2si.

Problem Cause

The two platforms have different CPU architectures, ALU implementations, operating systems, and compiler behaviors. x86 defines an “indefinite integer value” (0x8000000000000000) for floating‑to‑integer overflow, while Kunpeng simply clamps to the nearest representable limit (maximum or minimum).

Conversion tables (shown below) illustrate how double‑to‑long, double‑to‑unsigned‑long, double‑to‑int, and double‑to‑unsigned‑int behave on each architecture.

Other Issues

In a big‑data component test case, an expression expected to return 2^31 (0x80000000) on x86, which is the indefinite integer value. Kunpeng returns the maximum signed int 0x7FFFFFFF. External code that checks the return value with 2^32 misinterprets the x86 indefinite value as a normal integer.

Extended Knowledge

1. Floating‑point Representation

Modern computers follow the IEEE‑754 standard. Single‑precision (32‑bit) and double‑precision (64‑bit) formats consist of a sign bit, exponent, and fraction. The exponent uses a bias (127 for single, 1023 for double). Normalized numbers have an implicit leading 1.

Single‑precision: 1 sign, 8 exponent, 23 fraction bits.

Double‑precision: 1 sign, 11 exponent, 53 fraction bits.

Special values include infinities, NaN, and subnormals (when exponent is all zeros).

IEEE‑754 defines four rounding modes: round‑to‑nearest (ties‑to‑even), round‑toward‑+∞, round‑toward‑‑∞, and round‑toward‑0.

2. Two’s‑Complement Integer Representation

Integers are stored in two’s‑complement form; the same hardware can add/subtract signed numbers without separate logic. Example: a 4‑bit two’s‑complement pattern 1011 represents –5 (‑1·2³ + 0·2² + 1·2¹ + 1·2⁰ = –8 + 0 + 2 + 1 = –5).

Two’s‑complement allows addition circuits to handle both positive and negative numbers uniformly, simplifying circuit design.