Why Nvidia’s NVLink C2C Is Redefining GPU‑CPU Interconnects

Background

Nvidia leverages the low‑latency, high‑density NVLink‑C2C interconnect to construct SuperChip solutions that combine GPUs and CPUs while balancing performance and cost. The technology contrasts with traditional SerDes links and Chiplet‑to‑Chiplet (Die‑to‑Die) interconnects.

NVLink‑C2C Technical Characteristics

Latency : Uses 40 Gbps NRZ modulation with a bit‑error‑rate < 1e‑12, eliminating the need for forward error correction (FEC) and achieving sub‑5 ns interface latency. By contrast, 112 Gbps SerDes employs PAM4 modulation, incurs up to 20 ns latency and requires FEC, adding hundreds of picoseconds.

Bandwidth : Provides 900 GB/s inter‑chip bandwidth, while PCIe on the same GPU offers 128 GB/s.

Power Efficiency : Consumes 1.3 pJ/bit versus 5.5 pJ/bit for SerDes. At a 3.6 Tbps link, power is 4.68 W for NVLink‑C2C compared with 19.8 W for SerDes.

Density : Edge density of NVLink‑C2C is 3–4× that of SerDes (169 Gbps/mm² vs. 552 Gbps/mm²). However, its current edge density (281 Gbps/mm²) is slightly lower than SerDes (304 Gbps/mm²), indicating that higher density is not the primary driver.

Drive Capability : SerDes exhibits stronger drive capability, limiting NVLink‑C2C’s applicability in future high‑speed (>224 Gbps) scenarios where cable solutions become critical.

Cost : NVLink‑C2C offers lower area and power consumption than SerDes, allowing chip area savings for compute and cache. In large Chiplet assemblies, it can avoid expensive advanced packaging, reducing overall cost.

System‑Level Implications

NVLink‑C2C enables cache‑coherent memory operations between CPUs and GPUs, supporting Grace‑Hopper SuperChip configurations. The link’s low latency satisfies the stringent requirements for cache‑coherency, allowing Grace CPUs to act as memory controllers and I/O expanders for Hopper GPUs, delivering up to 4× I/O bandwidth and 5× memory capacity expansion.

These capabilities facilitate larger model training (via ZeRO off‑loading) and enable on‑chip inference of very large models by caching more data locally.

Cost Breakdown of Nvidia H100

GPU die cost (TSMC N4 process): ≈ $155 per chip.

HBM3 memory stack (six stacks from SK Hynix, Samsung, Micron): ≈ $2,000 total.

Combined GPU + HBM3 cost after CoWoS packaging: ≈ $723.

Memory accounts for > 60 % of total GPU cost; advanced packaging adds 3–4× the die cost.

Consequently, memory and advanced packaging dominate the cost structure, suggesting a design principle of avoiding unnecessary advanced packaging when possible.

Comparison with AMD and Intel GPUs

AMD relies more heavily on advanced packaging: MI250 uses wafer‑level bridge (EFB) and MI300 employs active‑interposer (AID) technology. Nvidia, by contrast, uses standard packaging with NVLink‑C2C to keep costs lower while preserving performance.

Intel’s Ponte Vecchio pushes packaging limits with 5 process nodes, 47 active tiles, and both EMIB 2.5D and Foveros 3D technologies, effectively serving as a testbed for advanced packaging. Intel’s Gaudi AI accelerators (Gaudi 2 on 7 nm, Gaudi 3 on 5 nm) illustrate a similar high‑performance, high‑cost approach.

Conclusions

NVLink‑C2C’s primary motivation is to meet low‑latency inter‑chip communication needs, offering a cost‑effective alternative to SerDes for many AI workloads. While its power and area advantages are clear, its drive capability and density limits may constrain future ultra‑high‑speed applications. The technology’s ability to enable flexible CPU‑GPU configurations and substantial memory capacity extensions makes it a key enabler for next‑generation AI systems.