Why RISC‑V Is Shaping the Future of Custom Chips in China and Beyond

Background and Drivers

Amid escalating trade wars, China’s need for a self‑reliant semiconductor supply chain, supportive government policies, and the rapid penetration of next‑generation information technologies, the industry seeks alternatives to complex, costly, and heavily licensed mainstream ISAs.

RISC‑V Technical Characteristics

RISC‑V is an open, royalty‑free instruction set architecture (ISA) designed for simplicity, modularity, and extensibility. Its streamlined encoding improves instruction‑fetch speed, while optional compressed extensions raise code density and decode efficiency. The reduced instruction set also lowers hardware implementation difficulty, especially in the memory access stage.

Global and Domestic Ecosystem

Internationally, multiple open‑source RISC‑V cores and commercial IP blocks have emerged, with major tech firms and startups contributing to a vibrant ecosystem. In China, companies such as Huawei, ZTE, and C‑SKY, as well as the RISC‑V Foundation, have launched the country’s first open‑source RISC‑V processor, the Honeybird E200, targeting ultra‑low‑power and ultra‑small‑area applications.

Industry Adoption and Applications

Key deployments include:

Ashling Systems & Imperas Software – integrated RISC‑V development tools.

CEVA’s RivieraWaves – Bluetooth/Wi‑Fi IP with optional RISC‑V MCU.

GreenWaves GAP8 – IoT processor built on RISC‑V.

Trinamic with Codasip – RISC‑V core for motion‑control.

Imperas RV64GC platform – high‑performance Linux‑capable RISC‑V solution.

Technical Comparison with Legacy ISAs

RISC‑V’s five‑stage pipeline (fetch, decode, execute, memory, write‑back) benefits from regular, compact encoding, which speeds up fetch and decode. Optional compressed instructions increase code density, reducing execution overhead. Although some performance trade‑offs exist in the memory stage, the overall hardware complexity is lower than that of ARM, MIPS, or x86.

Market Landscape

ARM dominates the embedded market, powering over 90% of smartphones and tablets, while x86 leads PCs. RISC‑V cores, however, offer higher performance, lower power consumption, and smaller silicon area, making them attractive for emerging IoT and AI workloads.

Implications for China’s Chip Industry

China’s semiconductor sector remains heavily import‑dependent (≈90% of chip value) and lacks a unified, sovereign ISA. RISC‑V’s open nature can reduce licensing costs, foster domestic IP creation, and enable customized, low‑power solutions for IoT and AI. Strategic recommendations include building a collaborative RISC‑V ecosystem, establishing testing and evaluation frameworks, and elevating RISC‑V development to a national strategic priority.