Will ASICs Overtake GPUs? How AWS and Google Are Set to Win

ASIC Market Share Forecast

In 2026, ASIC chip shipments are projected to be about 7.7 million units, representing a 45% market share. The share is expected to exceed that of GPUs, reaching 58% in 2027 and about 73% by 2030.

Manufacturing and Packaging Outlook

TSMC’s CoWoS capacity is expected to reach 2.66 million wafers in 2027, an 87% year‑over‑year increase. Within this capacity, the proportion allocated to ASIC manufacturers is projected to rise from 28% to 32%.

AWS Chip Development Timeline

In 2015, Amazon acquired Annapurna Labs for roughly $350 million. The acquisition aimed to reduce costs. In 2017, Amazon launched Nitro, offloading networking, storage, virtualization, and security isolation from the CPU to dedicated chips. In 2018, AWS introduced the ARM‑based Graviton CPU. In 2019, the inference chip Inferentia entered the AI market, followed by the training chip Trainium in 2021, which was merged with the inference line in 2023.

Trainium has released three generations: the first focused on cost replacement, the second added single‑card capability and large‑model training, and the third introduced system‑level interconnect to challenge GPU clusters.

In the Scale‑up network, Trainium 2 used a 2D/3D Torus topology similar to Google’s approach, but the torus structure is not optimal for MoE models; a 3D Torus can encounter bandwidth bottlenecks under overload. To address this, Trainium 3 switched from the torus to a switched architecture, incorporating NeuronSwitch‑v1, which dramatically increased demand for exchange chips.

Google TPU Evolution

Google’s TPU design team was formed internally. TPU v1 (2015) served internal search, advertising, translation, and recommendation workloads. TPU v2 added training capability and was offered externally via Cloud TPU. TPU v3 further increased compute and memory bandwidth and introduced larger Pods. TPU v4 marked a watershed by adding Optical‑Circuit‑Switch (OCS), creating a “chip + optical interconnect + system scheduler” architecture for data‑center‑scale products. TPU v5 split training and inference lines, while TPU v6 represented a major upgrade for the Transformer era. TPU v7 (Ironwood) targets generative‑AI inference.

TPU v8t (training) can scale a single Pod to 9 600 chips, delivering a peak FP4 performance of 121 ExaFLOPS (three times the previous generation) and an inter‑chip ICI bandwidth of 19.2 Tb/s. It adopts a two‑layer, non‑blocking Virgo network, allowing a single cluster to connect over 134 000 chips and providing up to 47 petabits/s of bidirectional bandwidth.

TPU v8i (inference/agent) features a Pod of 1 152 chips with 288 GB HBM + 384 MB on‑chip SRAM (three times the previous generation) and an HBM bandwidth of 8 601 GB/s. It replaces the torus topology with a Boardfly topology, reducing the network diameter from 16 hops to 7 hops, cutting tail latency by 50%, and using on‑chip CAE engines to lower global‑operation latency by fivefold.

According to SemiAnalysis, a TPU v7 POD with 9 216 TPUs required 48 OCS switches (TPU:OCS = 192:1), whereas a TPU v8i POD uses a ratio of 58:1, indicating a substantial increase in OCS proportion.

Alibaba Pingtouge Chip Roadmap

On May 20 2026, Alibaba announced its AI chip roadmap. The new generation AI chip “Zhenwu M890” offers 144 GB memory, 800 GB/s inter‑chip bandwidth, and delivers three times the performance of the previous “Zhenwu 810E”. The accompanying ICN Switch 1.0 interconnect chip can assemble 128 AI chips into a super‑node server with peer‑to‑peer latency below 150 ns. Over the next two years, Alibaba plans to launch the more powerful “Zhenwu V900” and “Zhenwu J900” chips.

By May 2026, the Zhenwu series had shipped a cumulative 560 000 chips, serving more than 400 customers across 20+ industries, including China Telecom, FAW‑Group, and Pudong Development Bank. By Q1 2026, over 100 000 Zhenwu PPU cards were deployed on Alibaba Cloud’s public platform, and more than 30 automotive and autonomous‑driving companies were developing intelligent‑driving solutions based on these chips.

Revenue, Market Share, and Profitability

According to Alibaba’s 2025 shareholder letter, Amazon’s chip business ARR exceeded $20 billion in Q1 2026, representing triple‑digit year‑over‑year growth and accounting for roughly 15% of cloud revenue; if sold as a standalone business, it could reach $50 billion.

Graviton: From 2023 to 2025, more than half of AWS’s new CPU capacity each year was supplied by Graviton, and 98% of the top 1 000 EC2 customers benefited from its cost‑performance advantage.

Trainium: Primarily serving Anthropic and OpenAI, Trainium is expected to generate over $3 billion in revenue in 2025.

Google: TPU hardware is now being sold directly to select customers such as Thinking Machines Lab, Hudson River Trading, and Boston Dynamics; TPU revenue is projected to account for 18% of Google Cloud’s revenue in 2026, contributing nearly $17 billion.

Based on rental and sale price comparisons of Trainium 2, Nvidia H100, H200, B200, B300, and TPU v6—considering chip cost alone and ignoring rental discounts—both Trainium 2 and TPU v6 exhibit higher gross margins than Nvidia chips.

Projected financial impact: In 2025, Amazon’s Trainium chip revenue is estimated at $3.4 billion, raising its share of cloud revenue to 7% by 2027; AI IaaS revenue could reach 18.5% of total cloud revenue in 2027, driving roughly a 4% overall revenue growth rate. Google’s Cloud TPU revenue is expected to reach $17 billion in 2026, representing an 18% share of cloud revenue.