Focused on system technology, sharing cutting‑edge developments, innovation and practice, and analysis of industry tech hotspots.
This article explores how C++ programs start, detailing the role of the _start entry point, the initialization of global objects via .init_array, __libc_csu_init, and constructors, and provides practical techniques—including linking with crt files and using init_priority—to control and debug initialization order and avoid crashes.
This article explains the Management Component Transport Protocol (MCTP), its Linux address family implementation AF_MCTP, driver and network configuration steps, socket programming examples, debugging techniques, and real‑world applications for component monitoring and management in firmware ecosystems.
ByteFUSE, a user‑space FUSE‑based solution for ByteNAS, delivers low‑latency, high‑throughput, POSIX‑compatible storage across AI training, database backup, and search services by replacing NFS with a cloud‑native architecture that leverages CSI, RDMA, and kernel‑module hot‑upgrade techniques.
This article explains the principles behind HWAddressSanitizer (HWASAN), how it uses the AArch64 Top‑Byte‑Ignore hardware feature to provide lower‑overhead memory error detection than ASAN, and walks through practical examples, implementation details, and LLVM integration for C/C++ developers.
This article explains the Strict Aliasing Rule, how compilers use Type‑Based Alias Analysis (TBAA) for optimization, demonstrates LLVM’s metadata‑based implementation, introduces the TypeSanitizer tool for detecting aliasing violations, and offers practical guidance to avoid common pitfalls in C/C++ code.
This article explains the fundamentals of Linux memory allocation, introduces Jemalloc’s core algorithms and data structures, and provides concrete optimization steps—including arena tuning, tcache configuration, and slab size adjustments—to achieve measurable CPU savings in high‑concurrency C++ services.
This article investigates the performance degradation caused by DPDK memory fragmentation, explains the underlying heap and element management, presents detailed profiling and test results, and proposes two practical solutions that dramatically reduce allocation latency and improve overall system throughput.
This article explains the architecture and workflow of Intel's GPU render engine, covering the 3D pipeline, command streamer, fixed‑function units, execution units, URB handling, thread dispatch, shader stages, sampler state, and the Mesa driver implementation that translates OpenGL commands into hardware instructions.
This article details ByteDance's end‑to‑end design and engineering of a low‑overhead, continuous profiling system that collects, processes, and analyzes resource usage across a million‑scale data center, enabling precise performance optimization and significant CPU cost savings.
This article explains the rasterization pipeline of GPU‑based 3D rendering, covering model setup, orthographic and perspective projection, viewport transformation, triangle rasterization, bounding‑box optimization, depth buffering, and final pixel shading, using a simple two‑triangle example to illustrate each step.
