How CXL Can Break the AI Memory Wall and Boost Data‑Center Performance

AI large‑model development has dramatically increased the demand for both compute ("算力") and storage ("存力"), exposing a long‑standing "memory wall" where memory performance lags far behind processor speed. Transformer‑style models double their parameters roughly every two years, while GPU memory capacity only grows by a factor of two in the same period, causing processors to idle while waiting for data.

1. The Memory Wall Becomes Critical in the AI Era

Beyond raw compute, AI workloads require high "运力" – the ability to move data quickly between compute and memory. As memory bandwidth fails to keep up, processors spend more time idle, limiting overall system performance despite adding more cores or GPUs.

2. CXL Emerges as a High‑Speed Interconnect

Compute Express Link (CXL) is a new high‑speed interconnect designed to provide higher throughput and lower latency while enabling memory sharing across devices. Initiated by Intel, AMD and other partners, and supported by Google, Microsoft and many others, CXL creates a pooled memory architecture that can be dynamically allocated to meet workload demands.

3. Advantages Over PCIe

CXL latency is typically around 10 ns, an order of magnitude lower than PCIe’s ~100 ns.

CXL supports memory coherency, which PCIe lacks, enabling more efficient data sharing.

CXL address space can be cached, whereas PCIe address space is generally non‑cacheable.

Although PCIe enjoys a mature ecosystem, CXL’s technical benefits open a large space for future adoption.

4. Continuous Evolution of CXL Versions

Since the first release (CXL 1.0, March 2019), the specification has progressed through 1.1, 2.0, 3.0 and the latest 3.1 (Nov 2023). Each iteration adds features such as higher PCIe lane speeds (PCIe 5.0 → 6.0, 32 GT/s → 64 GT/s), more flexible switch topologies, expanded memory pooling, and trusted execution environments.

5. Broad Industry Adoption

The CXL Consortium, led by Intel, now includes over 255 members ranging from CPU, memory, storage and networking vendors. Major players are integrating CXL support into upcoming products, accelerating the ecosystem’s growth.

6. Three Types of CXL Devices

CXL defines three protocols:

CXL.io : based on PCIe 5.0, handles initialization, link management and register access.

CXL.cache : enables low‑latency caching of host memory on the device side.

CXL.mem : provides load/store access to memory attached to the device.

Correspondingly, the consortium defines three device classes: intelligent NICs (CXL.io), accelerators with attached memory such as CPUs, GPUs and FPGAs (CXL.cache), and memory expansion/pooling devices (CXL.mem).

7. Market Outlook and DRAM Dominance

Analyst Yole predicts that by 2025, about 60 % of data‑center servers will use CXL, rising to nearly 100 % by 2027. Total CXL market revenue is expected to exceed $15 billion by 2028, with DRAM accounting for roughly 79 % of that value ($12.5 billion). Companies such as Samsung and Hynix have already released CXL‑compatible DRAM modules, e.g., Samsung’s 128 GB CXL 2.0 module launched in May 2023.