Why CXL Interconnect Chips Are the Next Big Leap for Data Centers

1. Overview of CXL Interconnect Chip Industry

CXL interconnect chips are high‑speed interconnect devices built on the Compute Express Link (CXL) protocol. They use the PCIe physical layer to enable low‑latency data exchange among CPUs, GPUs and memory, mainly for memory expansion and pooling scenarios.

2. Industry Policies Supporting CXL

The development of CXL chips receives policy support at the national level, including tax reductions, financing assistance and standards formulation, which create favorable conditions for enterprises and promote technological innovation and industry upgrading.

3. Industry Chain Structure

The CXL chip industry chain is tightly integrated: upstream supplies technology and materials, the mid‑stage focuses on chip manufacturing and packaging, and downstream is driven by broad application scenarios. AI and big‑data workloads drive continuous innovation across the chain.

4. Downstream Demand in China’s Server Market

In 2024, China’s server market reached ¥2,492.1 billion, a 41.3 % year‑on‑year increase, creating strong demand for CXL chips that improve internal component communication and meet rising AI compute needs.

5. Global Market Outlook

Globally, the CXL market was about $4.3 million in 2024, expected to grow to $1.703 billion by 2030 with a compound annual growth rate of 170.2 % (2025‑2030). CXL MXC chips currently hold 58.1 % market share, and the MXC segment is projected to reach $973 million by 2030.

6. China’s Position

China accounted for over 25 % of global CXL demand in 2024 and is expected to exceed 30 % by 2030, driven by AI and data‑center investments.

7. Competitive Landscape

International players such as Samsung, SK Hynix, Micron and Intel are active in CXL, while domestic company Lanqi Technology has achieved breakthroughs in CXL memory‑expansion controllers, positioning it for global market share.

8. Future Trends

Since the CXL consortium’s inception in 2019, the specification has evolved to version 3.2. Future chips will aim for higher bandwidth, lower latency and stronger cache coherence to meet the stringent data‑transfer requirements of AI workloads.

Source: Huajing Industry Research Institute