The article explains how Linux kernel scheduling uses a hierarchical topology—balancing load and preserving cache affinity—by mapping real‑world multi‑core hardware structures such as sockets, dies, clusters, and NUMA nodes to sched_domain and sched_group, and shows how to inspect and tune this layout with CONFIG_SCHED_DEBUG and QEMU simulation.
This article provides a comprehensive overview of server CPUs, covering core components, operation stages, performance parameters, Intel TurboBoost, Xeon Scalable naming, Tick‑Tock development, multi‑core and many‑core designs, hyper‑threading, heterogeneous computing, and the differences between CISC and RISC architectures.
This article explains the Linux kernel scheduler's core concepts, walks through the initialization code of the 5.4 kernel (including run queues, scheduling classes, domains, and groups), and details how multi‑core and NUMA topologies are handled to achieve balanced CPU usage.
This article explains the concepts of serial and parallel computing, describes how parallelism divides tasks across multiple processors, discusses speedup metrics and Amdahl's law, and highlights practical limits of multi‑core performance in modern computer architectures.
The article explains CPU fundamentals, including its core components, fetch-decode-execute-writeback cycle, key performance metrics, Intel TurboBoost, Xeon naming conventions, the Tick‑Tock development model, multi‑core and hyper‑threading technologies, and compares CISC and RISC architectures alongside emerging industry trends.
This article introduces the Kunpeng processor’s NUMA architecture, contrasts it with traditional SMP designs, and presents a practical five‑step methodology for performance optimization, helping developers on Kunpeng platforms achieve better scalability and efficiency through targeted memory‑access tuning.
This article explains the fundamentals of CPUs, covering their core functions, internal components, operation stages, key performance metrics such as clock speed, multiplier and external frequency, as well as modern technologies like Turbo Boost, multi‑core, hyper‑threading, and the evolution of CISC and RISC architectures.
