Fundamentals of Server CPUs and Architecture Overview

Servers are high‑performance computers that provide services to client machines; a complete 182‑page PPT on server fundamentals is referenced for deeper study.

The CPU (central processing unit) is the computational and control core of a computer, composed of an arithmetic logic unit, control unit, registers, and the buses that connect them.

CPU operation follows four stages: Fetch, Decode, Execute, and Writeback, moving instructions from memory into the instruction register for processing.

Key performance metrics include clock speed (frequency), multiplier, and external frequency; clock speed equals external frequency multiplied by the multiplier, and higher frequencies generally yield better performance.

The distinction between external frequency and multiplier arose because CPU development outpaced other hardware, leading CPUs to use a base external clock for motherboard communication while the multiplier adjusts the working frequency.

Intel Turbo Boost (Intel睿频加速技术) enables CPUs to run above their nominal frequency by dynamically allocating performance resources as needed.

In July 2017 Intel introduced the Purley platform with the Xeon Scalable Processor line, replacing the E5/E7 naming with Platinum, Gold, Silver, and Bronze tiers, and using a SKU coding scheme where the first digit denotes the tier, the second the generation, and the last two the specific model.

Intel’s “Tick‑Tock” model alternates between process‑technology updates (Tick) and micro‑architecture updates (Tock) roughly every two years, balancing risk and innovation.

Multi‑core processors integrate multiple CPU cores on a single chip, while many‑core (32‑64 cores) designs are referred to as “crowd‑core”.

Hyper‑Threading (simultaneous multithreading) presents each physical core as two logical CPUs, allowing multiple threads to run concurrently on the same core.

Heterogeneous computing incorporates non‑x86 units such as GPUs, FPGAs, and NPUs to accelerate specific workloads, especially in cloud, big‑data, and AI scenarios.

CPU instruction set architectures fall into CISC (e.g., x86) and RISC (e.g., ARM, RISC‑V, MIPS); CISC offers complex instructions with high per‑instruction efficiency, while RISC provides simpler instructions, lower power consumption, and higher core counts.

RISC architectures excel in data‑center workloads with better energy efficiency but may lag in single‑thread performance compared to x86.

Major RISC players include ARM, RISC‑V, and MIPS, with various Chinese companies (Huawei, Feiteng, Loongson, etc.) developing CPUs based on these ISAs.

Chip performance is tied to manufacturing process nodes; TSMC leads with 7 nm technology, while Chinese fabs such as SMIC, Huahong, and Hua‑li are advancing toward 14 nm and beyond.