2026 AI Compute Center High‑Speed Interconnect Technical Report

1. Four Core Scenarios of Supernode High‑Speed Interconnect

Supernodes are the core compute units of gigawatt‑scale AI centers and typically use a "Scale‑up + Scale‑out" hybrid topology. The report decomposes supernode interconnect into four scenarios—compute‑node, switch‑node, intra‑cabinet, and inter‑cabinet—and provides technical routes and recommended solutions for each.

Compute‑node interconnect : focuses on 4‑16 XPU cards within a node, reviewing high‑density multi‑lane cable assemblies, near‑package copper (NPC) and near‑package optical (NPO) solutions, and the ongoing upgrade of PCIe‑based high‑speed cables.

Switch‑node interconnect : tracks bandwidth growth from 25.6 Tbps to 102.4 Tbps and lane rates from 56 Gbps to 224 Gbps, analyzing the evolution of NPC/CPC copper and NPO/CPO optical paths.

Intra‑cabinet interconnect : describes the shift from traditional PCB back‑plane to cable‑tray, orthogonal mid‑plane, and fully orthogonal architectures, detailing structural features, tolerance design, and floating solutions, and cites representative deployments such as NVIDIA NVL72‑144, ByteDance Dayu, Baidu Tianchi, Huawei Cloud Matrix 384, Alibaba Pankiu AL128, and Sugon Scale X640.

Inter‑cabinet interconnect : compares DAC, ACC, AEC copper solutions with AOC and pluggable optical modules, defining selection strategies based on distance and bandwidth requirements.

2. End‑to‑End Implementation Path – Connectors, PCBs, and Cables

The report systematically covers the engineering implementation for the 56 Gbps‑to‑224 Gbps lane‑rate range.

Connector form factor : press‑fit holes shrink to ~0.25 mm, and SMT/BGA/LGA pad spacing tightens to ≤0.6 mm to preserve impedance continuity and signal integrity in high‑bandwidth scenarios.

High‑speed connectors : includes 56 Gbps, 112 Gbps, and 224 Gbps back‑plane connectors, internal high‑speed I/O (NPC, CPC for PCIe 5.0‑7.0), and external I/O (QSFP, QSFP‑DD, OSFP) covering DAC/ACC/AEC transmission distances.

High‑speed PCB materials : specifies dielectric loss (Df) requirements per speed tier and contrasts domestic versus foreign material selections to guide signal‑integrity design.

High‑speed raw cables : describes evolution from single‑layer to double‑layer, foam‑insulated, and dual‑core extruded structures; impedance tolerance tightens from ±5 Ω to ±2 Ω; intra‑pair skew improves to 2‑5 ps/m; SDD21 bandwidth reaches 110 GHz.

The report also lists mainstream product series from companies such as AVIC Optoelectronics, Qinghong Electronics, Huafeng Technology, and Lixun Technology, providing both technical depth and engineering practicality.

3. Outlook to 448 Gbps – Coexistence of Copper and Optical

Looking ahead to the next generation, the report predicts a single‑channel rate of 448 Gbps and outlines two parallel development paths.

Copper interconnect : advances in coding (PAM4/PAM6/PAM8), system architecture, product structure, and raw materials. CPC (co‑packaged copper) achieves >30 % link‑loss reduction and 30‑50 % power savings versus optical modules, cutting system cost by >15 %.

Optical interconnect : moves pluggable optical modules toward the 1.6 T standard and LPO evolution, gradually transitioning to NPO and CPO. CPO co‑packs the optical engine with the electrical chip, dramatically increasing bandwidth density while lowering BER and power, and breaking panel‑IO density limits.

The long‑term industry pattern will be a stable “copper‑optical coexistence” where copper handles short‑reach, cost‑sensitive links and optical serves long‑reach, high‑bandwidth connections, with deep application‑level synergy.