Anthropic’s latest blog reveals that its Claude models now write over 80 % of its code, have tripled productivity, and dramatically improve success rates, suggesting a recursive self‑improvement trajectory that could reshape AI development and prompts the company to call for a verifiable slowdown.
The Ling Sheng supercomputer topped the TOP500 with a 2.19 EFLOPS all‑CPU design, eschewing GPUs, achieving 84.4% scaling efficiency across millions of cores, high energy efficiency, and demonstrating a full‑stack domestic alternative that reshapes the global high‑performance computing landscape.
Anthropic’s internal report reveals that Claude now writes over 80% of its code, engineers’ productivity has jumped eight‑fold, and recursive self‑improvement is becoming a real risk, prompting the company to urge a worldwide slowdown of advanced AI development.
Anthropic’s internal data shows AI models are rapidly self‑improving—Claude now writes over 80% of its code, boosts engineer productivity several‑fold, and speeds up tasks dramatically—prompting a pause proposal and three possible future trajectories for AI development.
Anthropic’s internal report reveals that its Claude model now writes over 80% of the company’s code and boosts engineer output eight‑fold, providing concrete evidence of rapid recursive self‑improvement and prompting the firm to urge a worldwide slowdown of frontier AI research while outlining three possible future scenarios.
Anthropic’s internal data shows that AI‑generated code now accounts for over 80% of its codebase, with engineer productivity up eight‑fold, success rates climbing from 26% to 76%, and AI agents fixing complex bugs in hours—prompting a call for a coordinated pause if self‑improvement accelerates beyond control.
Anthropic’s internal report shows that its Claude model now writes over 80% of merged code and boosts engineer output eightfold, evidencing rapid recursive self‑improvement, while the company urges a worldwide pause on large‑model research and discusses potential future scenarios, risks, and the need for coordinated governance.
WorldCache separates cacheable and recomputable tokens in diffusion world models using curvature‑based classification and a chaotic‑prioritized adaptive skipping schedule, achieving up to 3.7× speedup on HunyuanVoyager‑13B and Aether‑5B without extra memory or retraining while preserving visual quality.
In 2026 the GPU market has shifted from Nvidia's lone dominance to a competitive arena where Nvidia, AMD, and Intel vie with emerging Chinese players and cloud‑vendor chips, emphasizing architecture, energy efficiency, chiplet packaging, and software ecosystems over sheer core count.
Within three weeks of GPT‑5.5’s launch, internal code for GPT‑5.6 surfaced, prompting OpenAI to unveil a 2‑3× “ultrafast” mode and a two‑month free Codex offer worth $400 to lure Claude Code users, sparking a high‑speed AI competition with Anthropic’s Opus 4.7 Fast and highlighting a self‑reinforcing acceleration loop toward ASI.
MIT researchers introduce DRiffusion, a draft‑and‑refine parallel framework that uncovers intrinsic parallelism in diffusion models, delivering 1.4–3.7× speedup on three GPUs while preserving near‑lossless image quality across Stable Diffusion 2.1, SDXL and SD3 evaluated on MS‑COCO.
This article explains how Baidu's new GLM-5 large model is adapted to the Kunlun P800 XPU, detailing the async reinforcement learning framework Slime, optimization techniques like INT8 quantization and tensor‑parallelism, and provides step‑by‑step deployment commands using the open‑source vLLM‑Kunlun plugin.
Baidu Baige’s enhanced veRL framework dramatically boosts video frame rates and resolution limits, cuts training time, reduces memory usage, and improves model accuracy by leveraging context parallelism and optimized attention on Ampere GPUs for multimodal mixed‑training scenarios.
This article examines the architectural differences between Scale‑Out and Scale‑Up networking, compares PCIe, NVLink, UALink, Infiniband and RoCE, and explains why high‑bandwidth, low‑latency GPU interconnects like NVLink are essential for modern AI and HPC workloads.
The article analyzes Nvidia's 2023 Blackwell GPU series and GB200 NVL72 architecture, detailing their advanced 3‑4nm manufacturing, redesigned CUDA cores, next‑gen ray‑tracing and DLSS upgrades, massive compute and memory bandwidth gains, NVLink Gen5 improvements, and the diverse GB200 product configurations for high‑performance AI workloads.
The paper introduces Single Trajectory Distillation (STD), a novel training framework that aligns full PF‑ODE trajectories from a fixed noisy state, uses a Trajectory Bank to cut training cost, and adds an Asymmetric Adversarial Loss to markedly improve style consistency and aesthetic quality while accelerating image and video style‑transfer diffusion models.
HBM5 introduces a 3D near‑memory computing architecture that vertically stacks DRAM dies and integrates compute units within the memory stack, dramatically boosting bandwidth, reducing data‑movement power, and delivering significant performance and energy‑efficiency gains for AI, high‑performance computing, and data‑center workloads.
This article explains how data‑center switches are classified, the key components and performance metrics of Ethernet switch chips, market growth trends, the shift from OEO to full‑optical OCS designs, and how RDMA technologies like InfiniBand and RoCEv2 enable the low‑latency networking essential for large‑scale AI training.
In March 2024 Nvidia unveiled the Blackwell GPU family and the GB200 NVL72 architecture, featuring 3‑4 nm processes, redesigned CUDA cores, next‑gen ray‑tracing, upgraded DLSS, massive FP16/FP8 compute gains, 8 TB/s memory bandwidth, and NVLink Gen5, while also presenting complex power, cooling, and packaging challenges for large‑scale AI deployments.
This article compares NVIDIA’s China‑specific B30 and high‑end H20 GPUs, detailing their CPU/CPU architecture updates, memory technologies, architectural differences, performance metrics, power and cooling characteristics, and price positioning, to help enterprises and developers choose the most suitable accelerator for AI and deep‑learning tasks.
NVLink, NVIDIA's high‑bandwidth interconnect introduced with the P100 GPU, replaces PCIe by offering significantly higher data rates and lower latency for GPU‑GPU and GPU‑CPU communication, and has evolved through multiple generations to support modern AI and high‑performance computing workloads.
At HPCA 2025, two standout papers—UniNDP, a unified compilation and simulation tool for near‑DRAM processing architectures, and WarpDrive, a GPU‑based fully homomorphic encryption accelerator leveraging Tensor and CUDA cores—demonstrate significant performance gains for AI workloads and privacy‑preserving computation.
DeepSeek’s Open‑Source Week unveiled five high‑performance projects—FlashMLA, DeepEP, DeepGEMM, DualPipe/EPLB, and 3FS—each delivering novel GPU optimizations, communication kernels, matrix‑multiplication libraries, parallelism strategies, and a distributed file system that together dramatically accelerate large‑scale AI training and inference workloads.
DeepGEMM is an open‑source FP8‑precision GEMM library that delivers up to 1350 TFLOPS on NVIDIA Hopper GPUs, offering JIT‑compiled, lightweight code (~300 lines) for dense and MoE matrix multiplication, with easy deployment, configurable environment variables, and performance advantages over CUTLASS for large AI models.
Large‑model inference engines convert prompts into responses via a Prefill stage and an autoregressive Decoder, measured by TTFT and TPOT, and Baidu’s AIAK suite improves TPOT by separating tokenization, using static slot scheduling, and asynchronous execution, cutting token‑interval latency from ~35 ms to ~14 ms and boosting GPU utilization to about 75 % while also leveraging quantization and speculative execution for higher throughput.
This article presents the YiNian LLM framework, detailing how KVCache, prefill/decoding separation, continuous batching, PageAttention, and multi‑hardware scheduling are used to speed up large language model inference while managing GPU memory and latency.
Target‑Driven Distillation (TDD) is a multi‑goal distillation method that flexibly selects short‑range target steps and decouples guidance during training, enabling 4‑to‑8‑step diffusion generation that preserves high‑resolution detail, works with LoRA, ControlNet, InstantID, and outperforms existing consistency distillation techniques in speed and quality.
This article explains the mGPU solution that virtualizes NVIDIA GPUs for containers, detailing its driver architecture, compute and memory isolation mechanisms, performance benchmarks on ResNet‑50 inference, and how it boosts GPU utilization by over 50% for AI and high‑performance computing tasks.
Quantum computing promises exponential parallelism and lower energy consumption, offering a disruptive solution to AI’s compute limits; with mature hardware‑software infrastructure, diverse technology roadmaps, emerging cloud platforms, and a market projected to grow from $4.7 billion in 2023 to over $8 trillion by 2035, it is poised to transform sectors such as finance, chemicals, and life sciences.
The article analyzes Nvidia's latest AI‑focused hardware and software breakthroughs showcased at ComputeX 2024, detailing how GPU‑CPU hybrid architectures, new libraries, and high‑speed interconnects like NVLink dramatically boost performance while keeping power and cost growth modest.
Hyper‑SD introduces a trajectory‑segmented consistency distillation framework that combines trajectory‑preserving and trajectory‑reconstruction strategies, integrates human‑feedback learning and score distillation, and achieves state‑of‑the‑art low‑step image generation performance on both SD1.5 and SDXL models.
This article explains the basic functions of CPUs and GPUs, their advanced capabilities and real‑world applications, and compares their architectures, processing models, and roles in environments such as IoT, mobile devices, Kubernetes, and AI workloads.
NVIDIA’s comprehensive LLM ecosystem combines the full‑stack NeMo Framework for data curation, distributed training, fine‑tuning, inference acceleration with TensorRT‑LLM and Triton, plus Retrieval‑Augmented Generation and Guardrails, enabling efficient, low‑latency, knowledge‑grounded model deployment across clusters.
SDXL‑Lightning, a new diffusion‑based text‑to‑image model from ByteDance, uses Progressive Adversarial Distillation to cut inference steps to as few as 2 while maintaining high resolution and fidelity, offering ten‑fold speed gains, open‑source access, and compatibility with SDXL, ControlNet, and ComfyUI.
PAI‑TorchAcc, an Alibaba Cloud AI platform accelerator, offers a seamless PyTorch interface that integrates HuggingFace models and employs LazyTensor‑based static graph conversion, multi‑strategy distributed training, and extensive GPU optimizations to dramatically boost throughput for 1B‑175B parameter models, surpassing PyTorch native and Megatron‑LM performance.
Ant Group’s newly open‑sourced ATorch library extends PyTorch with a layered architecture and automated resource‑aware strategies, boosting large‑model training efficiency up to 60% utilization, enhancing stability, and delivering significant throughput gains across multi‑node, multi‑GPU deployments.
This guide explains how to set up Alibaba Cloud's ACK environment, install the Cloud Native AI Suite, configure TensorRT, and run Stable Diffusion with dramatically reduced latency and memory usage, including detailed commands, performance metrics, and reproducible code snippets.
The article outlines the accelerating demand for high‑performance computing driven by AI, AR/VR, biotech and other workloads, examines the limits of Moore's law, and presents emerging solutions such as advanced chip architectures, chiplet integration, near‑memory/in‑memory computing, and distributed xPU‑based systems for scalable, efficient compute.
The 2023 Open Acceleration Specification AI Server Design Guide details the hardware architecture, OAM module and UBB board specifications, cooling, management, fault diagnosis, and software platform needed to build high‑performance, scalable AI compute clusters for large‑model training.
The article explains the various AI‑capable chips such as CPUs, GPUs, FPGAs, NPUs, and TPUs, compares their performance and efficiency, describes heterogeneous CPU+xPU solutions, and provides market share data while highlighting the growing adoption of specialized AI accelerators.
Since Nvidia's CEO highlighted DPUs as the third core chip for data centers in 2020, the technology has rapidly advanced, reshaping semiconductor markets, introducing CPU‑DPU‑GPU task partitioning, and driving a booming ecosystem highlighted by the 2023 DPU Summit in Beijing.
This article examines the highly concentrated DPU market, highlighting the dominant global vendors Nvidia, Broadcom and Intel, and provides a detailed analysis of emerging Chinese manufacturers—including NebulaX, Paratus, xFusion, Chiplet, and K2—covering their architectures, performance claims, and strategic positioning.
This article provides a comprehensive overview of Computing‑in‑Memory technology, covering its definition, historical evolution, performance advantages over traditional von Neumann architectures, various technical classifications, storage‑media choices, market drivers, and its pivotal role in AI and big‑data workloads across edge, cloud and automotive domains.
DeepMind’s AlphaFold inspired Uni‑Fold, now accelerated with Alibaba Cloud’s PAI platform, can predict protein structures up to 6.6k amino acids—covering 99.992% of known sequences—delivering ten‑minute inference for SARS‑CoV‑2 spike trimers and setting new performance benchmarks for AI‑driven structural biology.
Baidu Intelligent Cloud’s new Cloud‑native AI 2.0 platform tackles AI engineering bottlenecks by offering hybrid‑parallel large‑model training, flexible GPU virtualization, and an AI Accelerate Kit that boosts training efficiency over 50 % and cuts inference latency up to 63 %, raising GPU utilization from ~13 % to about 50 %.
Xiaohongshu, partnering with Huawei HMS Core, now runs on‑device super‑resolution for short videos, instantly upscaling 540p to 1080p and enhancing 720p content using GPU/NPU via HiAI, cutting bandwidth and stutter while keeping power use low across hundreds of Huawei devices.
The article provides a detailed technical analysis of NVIDIA's Hopper‑based H100 GPU, covering its 4 nm process, 800 billion transistors, GPC/TPC hierarchy, new FP8 Tensor Cores, Transformer engine, Tensor Memory Accelerator, and the resulting six‑fold performance jump over the previous A100 generation.
The article presents a detailed technical review of Kunlun Chip's XPU‑R AI accelerator, covering its evolution from early FPGA prototypes to the current 7nm, 256 TOPS chip, the architectural choices that address AI workload demands, performance advantages over CPUs/GPUs, and the product ecosystem supporting diverse AI scenarios.
This article details the design and implementation of sparse computation in Alibaba’s MNN inference engine, covering weight sparsity techniques, block‑sparse layouts, performance benchmarks on MobileNet models versus XNNPack, and real‑world deployment cases that demonstrate significant speedups and memory savings on mobile CPUs.
The 2021 China DPU Industry Development White Paper outlines DPU’s key use cases across data centers, cloud, security, AI, edge, storage and streaming, analyzes the competitive landscape among major vendors, and projects rapid global and Chinese market growth through 2025.
This report examines the role of data‑center networking in computational power, outlines factors driving full‑Ethernet evolution, and details the typical features, performance gains, and future directions of hyper‑converged data‑center network architectures.
At the Hangzhou Cloud Expo, Alibaba introduced its first self‑developed AI processor, the Hanguang 800, which delivers up to 78,563 inferences per second on ResNet‑50—four times faster than leading chips—and demonstrates remarkable energy efficiency, powering internal services and upcoming AI cloud offerings.
The Open Compute Project, backed by leading tech giants, is driving open‑hardware standards, accelerating AI and edge computing, and fostering collaboration across data‑center operators, telecoms, and hardware vendors, as highlighted by the upcoming OCP China Day conference.
This article explains NVIDIA's NVLink interconnect technology, covering its history, protocol layers, bandwidth advantages over PCIe, topologies such as the HGX-1/DGX-1 mesh, the NVSwitch extension, and performance gains for deep‑learning and high‑performance computing workloads.
In his 2018 Trusted Cloud Conference talk, Tencent FPGA expert Zhang Heng explained how the rapid growth of data and AI workloads drives data‑center and cloud operators to adopt FPGA acceleration for its high‑throughput, low‑latency, programmable performance, citing Tencent’s successes in image transcoding, content‑moderation, AI inference and gene‑sequencing, while outlining ecosystem challenges and future plans for scalable cloud‑FPGA services.
Tencent’s intelligent machine‑learning platform achieved a world‑record by training AlexNet in 4 minutes and ResNet‑50 in 6.6 minutes on ImageNet, using large batch sizes, mixed‑precision, LARS optimization, hierarchical synchronization, gradient fusion, and pipeline I/O techniques to overcome accuracy and scalability challenges.
