This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.
The article analyzes China’s Xinchuang hardware sector, forecasting a market size of 7.89 trillion yuan by 2026, examining shifts toward high‑performance domestic CPUs, comparing CISC (x86) and RISC (ARM, LoongArch, SW_64) instruction sets, and evaluating the strengths, licensing models, and ecosystem challenges of six major Chinese CPU manufacturers.
This article compares the major instruction set architectures—x86, ARM, and RISC‑V—explaining their CISC versus RISC philosophies, historical evolution, technical trade‑offs, and the current market landscape of domestic and global CPU vendors.
This article reviews recent decades of CPU performance improvements and semiconductor process advances, explains current CPU architectures, instruction set evolution, and how these trends influence software development practices, including parallelism, SIMD, multithreading, and power‑efficiency considerations.
This article provides a comprehensive overview of CPU fundamentals, covering core concepts such as clock speed, external frequency, front‑side bus, multiplier, bit and word length, cache hierarchy, instruction sets, voltage levels, manufacturing processes, pipelines, superscalar execution, SMP, multicore designs, multithreading, hyper‑threading, and NUMA technology.
This article explains the fundamental principles of how computers operate, covering the basic architecture of CPUs and memory, the role of buses and registers, instruction sets, compiler translation, cache hierarchies, storage layers, and the impact of 32‑bit versus 64‑bit designs.
The article provides a comprehensive overview of China’s domestic CPU ecosystem, explaining the role of CPUs as the digital foundation, comparing CISC and RISC instruction sets, and detailing the product lines and strategies of major manufacturers such as Huawei Kunpeng, HaiGuang, Feiteng, and Loongson, while concluding with market trends and competitive analysis.
This article explains the basic principles of computer architecture, covering CPU operation, memory hierarchy, cache levels, instruction sets, compilation, endianness, and related concepts such as simulators and operating system interactions, illustrating how simple instructions enable complex computations.
This article explains which instruction sets support atomic operations, detailing the principles behind x86’s LOCK prefix and ARM’s exclusive load/store mechanisms, illustrating how single‑processor and SMP systems handle atomicity, and showing Linux kernel implementations for atomic increment and compare‑and‑swap.
This tutorial guides readers through installing a DOS environment, writing and analyzing a simple 8086 assembly program, understanding pseudo‑instructions, registers, instruction categories, execution flow, and data addressing, providing links and code examples for hands‑on learning.
This article explores whether modern CPUs contain undocumented or hidden instructions, explains the challenges of searching the variable‑length x86 ISA, presents a depth‑first algorithm that skips irrelevant bytes, shows how to infer instruction length using page‑fault side‑effects, and reveals discovered hidden opcodes on Intel and AMD processors.
This article provides a comprehensive overview of server CPUs, covering core components, operation stages, performance parameters, Intel TurboBoost, Xeon Scalable naming, Tick‑Tock development, multi‑core and many‑core designs, hyper‑threading, heterogeneous computing, and the differences between CISC and RISC architectures.
The article narrates a CPU's journey from a naïve element‑wise increment loop to the adoption of SIMD, MMX, SSE, and AVX instruction sets, illustrating the motivations, challenges, and architectural decisions behind parallelizing integer and floating‑point operations.
The article introduces LoongArch, Loongson's self‑defined RISC instruction set architecture, detailing its evaluation approval, instruction count, format extensions, binary translation compatibility with MIPS, x86, ARM and RISC‑V, ecosystem plans, IP core updates, and the company’s strategy to build a domestic CPU ecosystem.
An overview of the CPU’s pivotal role in IT systems leads into a four‑point framework for domestic processors, covering ARM’s market dominance, the semiconductor supply chain, three development pathways—X86 licensing, ARM licensing, and self‑designed architectures—and the security‑driven outlook shaping China’s future CPU landscape.
Linus Torvalds lambasts Intel’s AVX‑512 extension as a ‘power virus’, arguing it bloats CPUs, serves only niche benchmarks, and harms everyday performance, while noting Intel’s recent move to limit AVX‑512 to large cores in Alder Lake and recalling his past clashes over Intel’s security patches.
This article provides a comprehensive overview of the ARMv8‑A architecture, explaining its RISC characteristics, execution states, instruction sets, register usage, and addressing modes, helping readers grasp the fundamentals needed to run operating systems like openEuler on ARM‑compatible servers.
This article explains how a CPU executes programs through the fetch‑decode‑execute cycle, describes instruction sets, registers, pipelines, superscalar and multithreaded designs, and details the cache hierarchy from registers to L3, providing a comprehensive overview of modern processor fundamentals.
This article explains the fundamental differences between RISC and CISC architectures, reviews the historical development and technical characteristics of processors such as MIPS, ARM, and x86, and discusses why China’s Loongson chips favor the MIPS instruction set over alternatives.
This article explains the core principles of CPU operation, covering the fetch‑decode‑execute cycle, instruction sets, registers, pipeline and superscalar designs, multithreading and multicore behavior, as well as cache hierarchy from registers through L1‑L3, illustrating how these mechanisms affect program execution.
This article introduces the fundamentals of x86 assembly language, explaining why low‑level code is needed, the history of assembly, CPU registers, the heap and stack memory models, and walks through a complete example with detailed explanations of each assembly instruction.
This article provides a comprehensive visual overview of CPU architecture, instruction sets, operating system purposes, programming layers, privilege rings, execution modes, user interfaces, and the distinction between ABI and API, helping readers grasp core computing concepts in a structured manner.
