How DPU Technology is Transforming Cloud Data Centers: From NICs to SoC

Evolution Stages of Network Interface Cards (NICs)

1. Traditional NIC : ASIC‑based implementation of PHY and MAC layers. Provides basic packet send/receive and limited hardware offloads such as CRC, TSO/LSO, VLAN tagging, SR‑IOV and QoS. Bandwidth has progressed from 100 Mbps to 10/25/100 Gbps.

2. SmartNIC : Adds data‑plane offload (e.g., OVS/vRouter fast‑path, RDMA, NVMe‑oF, IPsec/TLS) using an FPGA or an integrated FPGA+lightweight CPU. The host CPU still manages the control plane.

3. FPGA‑Based DPU : Combines a SmartNIC with a general‑purpose CPU (e.g., Intel Core) in an FPGA+CPU architecture. Enables both data‑plane and control‑plane offload and programmable extensions.

4. DPU SoC : A single‑chip solution that integrates ASIC accelerators and a CPU core, delivering rich offload capabilities, high throughput, lower power consumption and full programmability for cloud workloads.

Hardware challenges for FPGA‑Based DPUs include limited PCIe board area and high power/thermal budgets, which drive the migration toward single‑chip DPU SoCs.

Concept of a Data Processing Unit (DPU)

A DPU embodies the "software‑defined, hardware‑accelerated" paradigm. It contains dedicated data‑plane processing units for high‑throughput packet handling and general‑purpose cores for control‑plane orchestration, balancing performance with flexibility and allowing replacement of CPU‑heavy networking, storage and security functions.

NIC Development and Virtualization Methods

Traditional NICs support three VM connectivity models:

Kernel‑stack forwarding (traffic passes through the OS network stack).

DPDK user‑space driver bypass, copying packets directly to VM memory.

SR‑IOV virtual functions (VFs) passed through to VMs.

Increasing use of tunnel protocols (VxLAN) and virtual switches raises processing complexity, motivating SmartNIC adoption.

SmartNIC Offload Capabilities

SmartNICs retain basic NIC functions while offloading data‑plane workloads such as virtual switch fast‑path, RDMA, NVMe‑oF, and IPsec/TLS. This reduces host‑CPU cycles and improves cloud network throughput.

FPGA‑Based DPU Architecture and Limitations

The FPGA+CPU architecture accelerates networking, storage, security and control functions. Early products adopted this model for rapid market entry. However, as bandwidth scales from 25 Gbps to 100 Gbps, FPGA area and power constraints limit further throughput improvements.

DPU SoC Integration

DPU SoCs integrate ASIC accelerators with a CPU on a single die, offering high‑performance specialized engines and programmable cores. Benefits include reduced cost, lower power, support for VMs, containers and bare‑metal workloads, and unified resource management across cloud scenarios.

Major Cloud Provider DPU Deployments

AWS Nitro DPU

The Nitro system offloads networking, storage, security and monitoring to dedicated hardware (Nitro cards, a Nitro security chip and a lightweight Nitro hypervisor). This frees almost all server resources for customer workloads and enables up to 100 Gbps network performance for bare‑metal instances.

Nvidia BlueField DPU

After acquiring Mellanox, Nvidia released the BlueField series. BlueField‑3 provides up to 400 Gbps of network connectivity and supports software‑defined networking, storage, security and control functions, targeting AI and accelerated‑computing workloads.

Intel Infrastructure Processing Unit (IPU)

Intel offers two IPU families:

Oak Springs Canyon – FPGA‑based IPU built on Intel Agilex FPGA plus a Xeon‑D CPU.

Mount Evans – ASIC‑based SoC co‑designed with Google, featuring an ASIC data‑plane and a 16‑core ARM Neoverse N1 compute subsystem.

Both provide full infrastructure offload, reducing server‑CPU load and enhancing security.

Alibaba Cloud CIPU

Alibaba Cloud’s Cloud Infrastructure Processing Unit (CIPU) evolved from the MoC (Micro Server on a Card) concept. Successive generations added hardware offload for networking, storage and RDMA, culminating in a fully hardware‑offloaded DPU solution that underpins Alibaba’s next‑generation cloud architecture.

Volcano Engine DPU

Volcano Engine’s self‑developed DPU integrates hardware and software virtualization. It powers elastic bare‑metal and cloud servers (second‑generation EBM and third‑generation ECS instances), delivering high‑performance, secure and flexible compute.

Overall, the transition from basic NICs to programmable DPU SoCs reflects the industry’s drive for higher throughput, lower power consumption and greater programmability in modern data‑center architectures.

Code example

2.智能网卡(SmartNIC)。具备一定的数据平面硬件卸载能力，例如OVS/vRouter硬件卸载。硬件结构上以FPGA或者是带有FPGA和处理器内核的集成处理器(这里处理器功能较弱)来实现数据面硬件卸载。
3.FPGA+CPU的DPU网卡(FPGA-Based DPU)。兼具智能网卡功能的同时，可以支持数据面和控制面的卸载以及一定的控制平面与数据平面的可编程能力。硬件结构的发展上，基于FPGA增加了通用CPU处理器，例如Inte1 CPU。
4.DPU SoC网卡(Single-Chip DPU)。单芯片的通用可编程DPU芯片，具备丰富的硬件卸载加速和可编程能力，支持不同云计算场景和资源统一管理特性。