How Five Undergraduates Designed a 64‑bit RISC‑V Chip and Graduated with Their Own Processor

Project Overview

In 2020 five UCAS undergraduates designed and fabricated a 64‑bit RISC‑V processor‑SoC named NutShell (果壳). The chip was manufactured in SMIC 110 nm CMOS, boots Linux and the teaching OS UCAS‑Core, and the RTL is open‑sourced at https://github.com/OSCPU/NutShell.

Design Methodology

Hardware described in Chisel, chosen for higher productivity without quality loss.

Core derived from a teaching RISC‑V processor from Nanjing University; existing NEMU simulator and differential‑testing framework were reused.

Extensions added to satisfy Linux requirements: RV64IM, RVC, RVA, multiple privilege levels, hardware TLB, cache prefetch, SDRAM controller, and assorted I/O peripherals.

Development Timeline

Program “One Life One Chip” launched June 2019. After a four‑month intensive design phase, the layout was frozen on 19 Dec 2019 and the chip was sent to SMIC. The wafer returned in January 2020 despite COVID‑19 lockdowns.

Testing and Performance

Initial bring‑up ran the core at 50 MHz; after debugging an I/O bug affecting SD‑card access and incremental tuning, stable operation was achieved up to 350 MHz, supporting both Linux and the RT‑Thread RTOS.

Graduation Demonstration

On 2 June 2020 each student defended a thesis covering topics such as out‑of‑order execution, vector units, branch prediction, non‑blocking caches, and binary translation. The NutShell board successfully booted Linux during the defense.

Community Release

The design was submitted to the RISC‑V Global Forum and accepted for presentation on 3 Sept 2020. All source code, documentation, and layout files are publicly available at the GitHub repository above.

Future Work

The team plans to develop a high‑performance out‑of‑order RISC‑V core, building on the experience gained from the NutShell project.