Huawei's Hi1620 ARM Server Processor: Architecture, Specifications, and Roadmap
The article outlines Huawei's development of ARM‑based server CPUs, especially the 7nm Hi1620 processor, detailing its architecture, core counts, cache hierarchy, memory and I/O capabilities, and its significance for modern data‑center and cloud computing workloads.
For more than four years ARM has been striving to become a core component of modern servers, data centers, and cloud infrastructures, with notable deployments such as the Astra supercomputer at Sandia National Labs (ranked 205 in the TOP500) using ARM technology.
Huawei, a major technology company, leverages its consumer business group and the HiSilicon design team to create a wide range of custom hardware, from smartphone chips (Kirin) to modems, SSD controllers, PCIe controllers, and high‑performance enterprise processors.
At the SC18 conference Huawei showcased its first 7 nm ARM‑based server processor, the Hi1620, following earlier TaiShan generations (Hi1610, Hi1612 Cortex‑A57, Hi1616) that were designed for platform development and commercial deployment preparation.
The Hi1612, launched in mid‑2016, is a 64‑bit ARM server microprocessor fabricated on TSMC’s 16 nm process, integrating 32 Cortex‑A57 cores running at 2.1 GHz and supporting up to 256 GiB of four‑channel DDR4‑2133 memory.
The Hi1620 is built on the ARM v8.2 architecture, configurable with 24 to 64 cores per socket, each core equipped with 512 KB L2 cache and a shared 1 MB L3 cache, and manufactured using a 7 nm process.
Each core features 64 KB L1 data and 64 KB L1 instruction caches; the chip offers 40 PCIe 4.0 lanes (compared to 46 PCIe 3.0 lanes on Hi1616), supports CCIX, dual 100 GbE MACs, USB 3.0, and SAS connections. Memory is configured with eight channels, up to DDR4‑3200, and the processor can be used in up to four‑socket configurations with a coherent SMP interconnect delivering up to 240 GB/s bandwidth.
An architectural roadmap image illustrates the evolution of ARM server designs, and Huawei states that the Hi1620 will have a TDP range of 100 W to 200 W, with core counts adjustable for memory‑bound workloads, though challenges such as interconnect design and Ares micro‑architecture remain.
For further reading, see the linked article about the IBM OpenPower Foundation and Alliance.
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