The Evolution of Compute Power: From CPUs and GPUs to DPUs and Future Data‑Center Architectures

Computing power has risen from a technical metric to a core productive force, with data‑center infrastructures ranging from small enterprise clusters to massive facilities delivering storage, software, and compute services that underpin the global digital economy.

The load on processors is increasingly diversified; tasks are being offloaded from CPUs to in‑memory, near‑memory, and network‑level processing, reducing data‑movement energy and latency.

Computation is moving from a simple "edge‑cloud" model to an "edge‑cloud‑edge" continuum, incorporating fog and mist layers that allocate workloads to the most appropriate tier, much like hierarchical governmental administration.

Hardware architecture now combines general‑purpose CPUs with specialized accelerators (GPU, DPU, ASIC). GPUs dominate AI training, while DPUs emerge as the next‑generation data‑center engine for network, storage, and security workloads.

DPUs (Data Processing Units) act as CPU off‑load engines, handling high‑speed packet processing, encryption, and storage protocols, thereby freeing CPU cycles for application logic and reducing the so‑called "Datacenter Tax".

Modern DPU designs integrate heterogeneous cores: general‑purpose ARM cores for programmability and dedicated accelerators for tasks such as OLAP/OLTP, machine‑learning inference, and cryptographic operations, exemplified by the KPU‑based architecture from 中科驭数.

The KPU‑based DPU product line (e.g., SWIFT™‑2000M) combines a full TCP/IP stack, NVMe‑over‑TCP acceleration, and high‑performance PCIe interfaces to deliver ultra‑low‑latency storage networking.

Future directions emphasize building dedicated‑processor systems focused on the data plane, fusing innovative technologies (NVMe, RDMA, HBM, neural‑network acceleration), adopting domain‑specific languages for precise workload description, and pursuing vertical specialization before horizontal expansion.