Fei has over 10 years of development experience at Tencent and Sogou. Through this account, he shares his deep insights on performance.
This guide introduces CodeVideoX, a diffusion‑transformer based video generation model, explains its training and inference pipelines, and provides step‑by‑step instructions with API endpoints, required parameters, and example cURL commands for creating short AI‑generated videos.
This article introduces a new book 'Deep Understanding of Linux Processes and Memory' that systematically explains CPU, memory, and process scheduling principles, covering hardware fundamentals, virtual memory, Golang coroutines, container resource management, and performance optimization techniques.
The article explains that server memory modules contain more chips because they need ECC error‑correction, additional register and data buffer chips for RDIMM/LRDIMM designs, which increase chip count, improve signal integrity, and allow larger capacities.
This article explains how to invoke Go functions from C within the same process, covering the three‑step implementation, the required cgo compilation commands, the generated intermediate files, and the runtime mechanisms such as crosscall2 and stack switching that make cross‑language calls possible.
This article explains the physical structure of computer memory modules, interpreting label strings such as "2R*8" to describe ranks and chip bit-width, and details how chips, banks, and matrix cells are organized to support burst I/O and cache lines.
This article explains the architecture of server‑grade CPU memory controllers, covering memory channel counts, bandwidth calculations, the differences between UDIMM, RDIMM and LRDIMM modules, and the role of ECC in ensuring data integrity.
This article details the motivations, technology choices, step‑by‑step deployment of Typecho on a Tencent lightweight cloud server, domain registration, site theming, custom image‑processing plugins, HTTPS setup, content migration, and a concise checklist for building a dynamic personal technical website.
This article explains why ECC memory modules use an extra chip, how bit‑flip errors occur in 64‑bit CPU‑memory transfers, and how simple parity and Hamming‑code algorithms detect and correct single‑bit errors while only detecting double‑bit errors, illustrating the principles with diagrams and examples.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, with server chips being larger, more expensive, lacking integrated graphics, offering more cores, ECC memory, multi‑CPU interconnects, and lower base frequencies for stability.
This article explains how the glibc malloc implementation (ptmalloc) manages memory by using arenas, chunks, and various bin structures such as fastbins, smallbins, largebins, and unsorted bins, and describes the step‑by‑step allocation process performed by public_mALLOc and its helper functions.
