Fei has over 10 years of development experience at Tencent and Sogou. Through this account, he shares his deep insights on performance.
This article explains why ECC memory modules use an extra chip, how bit‑flip errors occur in 64‑bit CPU‑memory transfers, and how simple parity and Hamming‑code algorithms detect and correct single‑bit errors while only detecting double‑bit errors, illustrating the principles with diagrams and examples.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, with server chips being larger, more expensive, lacking integrated graphics, offering more cores, ECC memory, multi‑CPU interconnects, and lower base frequencies for stability.
This article explains how the glibc malloc implementation (ptmalloc) manages memory by using arenas, chunks, and various bin structures such as fastbins, smallbins, largebins, and unsorted bins, and describes the step‑by‑step allocation process performed by public_mALLOc and its helper functions.
This article explains the Intel Xeon server CPU naming conventions, outlines each generation from Skylake to Sapphire Rapids, and details the internal Mesh interconnect and external UPI bus that enable high‑core counts and multi‑CPU scalability in modern data‑center processors.
This article explains the motivations behind distributed databases in high‑risk industries, introduces Tencent Cloud's TDSQL as a market leader, and details its architecture—including load balancing, SQL engine, compute and storage separation, raft‑based strong consistency, lossless upgrades, high‑availability failover, and an intelligent DBA platform.
This article explains how Linux processes can share large data efficiently by creating a memory file with memfd_create, mapping it with mmap, and transferring the file descriptor over a Unix Domain Socket, while detailing the kernel mechanisms that enable true cross‑process memory sharing.
This article traces the evolution of CPUs by examining process node reductions, increasing integration of components, memory controller upgrades, PCIe advancements, and microarchitectural innovations that together shape modern processor performance and efficiency.
This article explains Intel's CPU naming conventions, the meaning of each part of a processor model string, the evolution of CPU generations from Haswell to Raptor Lake Refresh, and the internal micro‑architecture of a Kaby Lake i5‑7200U, illustrated with die diagrams and code examples.
This article explains how a Go hello‑world program starts, tracing the ELF entry point, runtime initialization, GMP scheduler setup, creation of the main goroutine, and the flow into the user's main function.
This article explains how AI-powered plugins like CodeGeeX can automate code writing, explain existing code, provide intelligent completions, and translate code between languages, helping developers dramatically improve productivity and reduce repetitive coding tasks.
