2030 AI Compute Chips: Three Technology Routes Battle for Dominance

According to Sullivan's 2026 Global Emerging AI Compute Chip & Future Key Technology Development Industry Research Report , China's AI compute chip market grew from ¥28.83 billion in 2021 to ¥208.8 billion in 2025 and is projected to reach ¥1,615.6 billion by 2030, representing a 48.8% CAGR from 2026–2030. Inference compute demand is expanding especially fast, with a 69.7% annual growth rate forecast for 2026–2030, fueling demand for low-power, low-latency chips.

The industry faces three core challenges: compute efficiency, generality, and scale-out capability. In response, global AI compute chips have split into two camps and three technical routes: the general-purpose GPGPU route, and the new compute chip camp comprising Dataflow and ASIC/DSA routes.

Route 1: ASIC/DSA (Domain-Specific Architecture)

Characteristics: Hardware and algorithm are deeply bound; redundant modules are trimmed, yielding excellent energy efficiency and cost but weaker generality, making it suitable for inference. Hardware circuitry is fixed, so algorithm iterations require extensive software adaptation.

Huawei Ascend – Representative Ascend series chips use DSA architecture. They build a hardware board–server–cluster system paired with the CANN full-stack software suite covering cloud, edge, and device. Strengths include large-scale AI cluster networking and a self-developed full-stack ecosystem, already deployed at scale in domestic intelligent computing centers.

Cambricon – First listed Chinese AI chip company; its Siyuan MLU series uses proprietary ASIC architecture covering cloud, edge, and endpoint. Focuses on inference while gradually strengthening training. Supports Chiplet multi-die packaging; continuously improves operator libraries and compiler toolchains for internet, finance, and transportation sectors.

Route 2: Dataflow (Software-Defined Hardware)

Characteristics: Reconfigurable compute arrays balance high energy efficiency with architectural flexibility. Chips natively support chip-to-chip RDMA, enabling low-cost 10,000-card clusters. Naturally suited for compute-network convergence, 3D integration, and wafer-scale integration; inference advantages are significant.

Qingwei Intelligence – Domestic reconfigurable dataflow leader from Tsinghua's reconfigurable computing team. Products: TX5 (edge), TX8 (cloud) RPU chips. Ranked third globally in 2025 dataflow revenue, behind only Google and Groq. Self-developed RAISA full-stack software supports CUDA migration and PyTorch/TensorFlow frameworks; participates in FlagOS open ecosystem. Chips feature direct chip-to-chip networking; deployed in 10+ domestic 1,000-card intelligent computing centers with cumulative shipments exceeding 30,000 units.

Zhonghao Xinying – Also in dataflow track, early commercialization stage; ranked fifth globally with smaller revenue scale.

Route 3: Domestic GPGPU (General-Purpose GPU)

Characteristics: Strong generality, adapts to both training and inference tasks, but faces diminishing returns from Moore's Law and overseas technology restrictions. Benchmarks against NVIDIA GPUs, pursuing compatibility with general ecosystems.

Moore Threads – Domestic GPGPU representative with proprietary MUSA full-stack architecture, balancing graphics rendering and AI compute. Targets cloud intelligent computing and edge scenarios; high capital-market recognition. Other players include Tianshu Zhixin and Biren Technology, focusing on large-model training; some already listed with high valuations.

The article includes 25 charts/diagrams illustrating market trends, architecture comparisons, vendor landscapes, and deployment scales (images referenced via URLs).