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Design Hub
Design Hub
Mar 29, 2026 · User Experience Design

How a Bedside Alarm Clock Reclaims the Night from Phones: Balmuda’s Thoughtful Design

The article examines how Balmuda, together with design studio LoveFrom, transformed the overlooked bedside clock into a carefully crafted, screen‑free device that solves the disruptive phone‑on‑the‑nightstand problem through minimalist lighting, curated soundscapes, and nuanced interaction, illustrating the power of deep design insight.

BalmudaProduct DesignUser experience
0 likes · 7 min read
How a Bedside Alarm Clock Reclaims the Night from Phones: Balmuda’s Thoughtful Design
Liangxu Linux
Liangxu Linux
Mar 26, 2026 · Fundamentals

Master STM32 Projects: From Schematics to Stable, Maintainable Code

This guide walks through the essential steps of STM32 development—from reading schematics and configuring CubeMX to structuring code, debugging with tools like J‑Link RTT, and optimizing performance, providing practical tips to avoid common pitfalls and build reliable embedded systems.

CubeMXSTM32code architecture
0 likes · 6 min read
Master STM32 Projects: From Schematics to Stable, Maintainable Code
Liangxu Linux
Liangxu Linux
Jan 26, 2026 · Fundamentals

Why I2C Needs Pull‑Up Resistors and How to Choose the Right Value

This article explains the open‑drain nature of I2C, why pull‑up resistors are essential for providing a high level, ensuring signal integrity and enabling wired‑AND logic, and offers practical formulas, recommended resistor ranges for different speeds, STM32 configuration examples, and debugging tips.

I2CSTM32bus communication
0 likes · 13 min read
Why I2C Needs Pull‑Up Resistors and How to Choose the Right Value
Architects' Tech Alliance
Architects' Tech Alliance
Jan 16, 2026 · Artificial Intelligence

Why Do GPUs and NPUs Produce Different FP16 Results? Uncovering AI Chip Precision Secrets

Engineers training large AI models often see noticeable FP16/BF16 result differences between GPUs and NPUs, and even between generations of the same chip, due to floating‑point representation limits, hardware design choices, software library implementations, compiler optimizations, and parallel execution nondeterminism.

GPUNPUai
0 likes · 10 min read
Why Do GPUs and NPUs Produce Different FP16 Results? Uncovering AI Chip Precision Secrets
Liangxu Linux
Liangxu Linux
Aug 17, 2025 · Fundamentals

From Specification to Silicon: The Complete Digital Chip Design Flow

This article provides a comprehensive, step‑by‑step overview of digital chip design, covering specification definition, system architecture, front‑end logic design, back‑end physical implementation, verification, sign‑off, and tape‑out, complete with diagrams and practical insights into each stage.

Chip DesignDigital ICEDA
0 likes · 21 min read
From Specification to Silicon: The Complete Digital Chip Design Flow
Meituan Technology Team
Meituan Technology Team
Aug 14, 2025 · Artificial Intelligence

How Meituan’s Smart Helmet Redefines Delivery Safety with AI‑Powered Design

Meituan’s first smart‑helmet article details hardware innovations that tackle delivery riders’ safety, comfort, and efficiency, covering stricter safety standards, sensor‑driven alerts, lightweight structures, advanced ventilation, three‑times longer battery life, noise‑cancelling audio, IPX6 waterproofing, and a data‑driven production line.

AI Safetydelivery efficiencyhardware design
0 likes · 24 min read
How Meituan’s Smart Helmet Redefines Delivery Safety with AI‑Powered Design
Architects' Tech Alliance
Architects' Tech Alliance
Aug 4, 2025 · Fundamentals

What Is an ASIC? Core Concepts, Design Flow, and Real-World Applications Explained

This article provides a comprehensive overview of ASIC technology, covering its definition, origins, design process, key parameters, core techniques, and major application domains such as data centers, AI, automotive, and more, while also comparing it to general‑purpose ICs and highlighting leading industry players.

ASICchip architecturehardware design
0 likes · 21 min read
What Is an ASIC? Core Concepts, Design Flow, and Real-World Applications Explained
Java Tech Enthusiast
Java Tech Enthusiast
Jul 20, 2025 · Fundamentals

How a DIY Enthusiast Built a Fully Functional CPU from Old Memory Chips

A YouTuber known as MINT documented the creation of EPROMINT, a complete 8‑bit CPU built from discarded memory chips and simple logic components, detailing its ALU design, modular architecture, custom instruction set, interrupt handling, video output, open‑source release, and plans for a C compiler.

Assembly LanguageDIY CPUhardware design
0 likes · 9 min read
How a DIY Enthusiast Built a Fully Functional CPU from Old Memory Chips
Liangxu Linux
Liangxu Linux
Feb 16, 2025 · Fundamentals

How Steve Wozniak Built the First Complete Computer System Solo in 1976

Steve Wozniak single‑handedly designed and built the Apple I in 1976, creating both the hardware using a Motorola 6800 CPU and 4 KB RAM and the software including a BASIC interpreter and a machine‑language monitor, demonstrating how one person could assemble a complete computer system before the era of modern development tools.

Apple ISteve Wozniakcomputer history
0 likes · 5 min read
How Steve Wozniak Built the First Complete Computer System Solo in 1976
Architects' Tech Alliance
Architects' Tech Alliance
Dec 2, 2024 · Artificial Intelligence

What Makes ASIC Chips the Powerhouse Behind AI? A Deep Technical Dive

This article provides a comprehensive technical overview of AI chips, focusing on ASIC technology—including its classifications, design trade‑offs, performance advantages, drawbacks, real‑world examples, and emerging market trends—while also summarizing related GPU, FPGA, and neuromorphic developments.

AI chipsASICTechnology Analysis
0 likes · 11 min read
What Makes ASIC Chips the Powerhouse Behind AI? A Deep Technical Dive
NetEase Cloud Music Tech Team
NetEase Cloud Music Tech Team
Feb 2, 2024 · Fundamentals

Apple Vision Pro: Hardware Overview, Spatial Design Principles, and Application Scenarios

Apple’s Vision Pro, a head‑mounted display launched in early 2024, combines a curved 3‑D glass front, dual‑eye micro‑OLED screens, M2 and R1 chips, extensive cameras and sensors, and a breathable headband to deliver low‑latency mixed reality via VisionOS’s windows, volumes and spaces, while emphasizing familiar UI, ergonomics, privacy through on‑device Optic ID, and enabling novel experiences such as immersive music‑app environments.

Apple Vision ProMixed RealitySpatial Computing
0 likes · 20 min read
Apple Vision Pro: Hardware Overview, Spatial Design Principles, and Application Scenarios
Liangxu Linux
Liangxu Linux
Jun 14, 2023 · Fundamentals

Why Do Modern CPUs Use an 8‑Bit Byte? Historical and Technical Reasons Explained

This article explores why the x86 architecture adopted an 8‑bit byte, examining historical decisions, character‑encoding needs, binary‑coded decimal compatibility, power‑of‑two advantages, and legacy compatibility, while clarifying the distinction between bytes and words in computer design.

binary representationbyte sizehardware design
0 likes · 14 min read
Why Do Modern CPUs Use an 8‑Bit Byte? Historical and Technical Reasons Explained
Architects' Tech Alliance
Architects' Tech Alliance
Mar 9, 2023 · Artificial Intelligence

In‑Depth Analysis of Tesla D1 Processor and Dojo Architecture

This article provides a comprehensive technical review of Tesla's D1 AI processor and Dojo super‑computer architecture, covering its data‑flow near‑memory design, RISC‑V‑like instruction set, matrix compute units, chiplet packaging, power‑management, cooling solutions, and the associated software compilation ecosystem.

AI ChipCompilation EcosystemDojo Architecture
0 likes · 23 min read
In‑Depth Analysis of Tesla D1 Processor and Dojo Architecture
IT Services Circle
IT Services Circle
Nov 18, 2022 · Fundamentals

How Steve Wozniak Single‑Handedly Built the First Complete Computer System (Apple I)

The article recounts how Steve Wozniak, inspired by the Homebrew Computer Club in 1975, single‑handedly designed and built the Apple I computer using a Motorola 6800 CPU, 4 KB memory, a BASIC interpreter and a machine‑language monitor, illustrating the challenges of creating a complete system in the 1970s.

Apple ISteve Wozniakcomputer history
0 likes · 6 min read
How Steve Wozniak Single‑Handedly Built the First Complete Computer System (Apple I)
Alibaba Cloud Infrastructure
Alibaba Cloud Infrastructure
Jul 5, 2022 · Fundamentals

High‑Performance Chiplet and Interconnect Architectures: Insights from the HiPChips Workshop at ISCA 2022

The HiPChips workshop at ISCA 2022 gathered leading academia and industry experts to discuss the motivations, recent research breakthroughs, technical challenges, and ecosystem efforts surrounding high‑performance chiplet and interconnect architectures for future computing systems.

Chipletcomputer architecturehardware design
0 likes · 10 min read
High‑Performance Chiplet and Interconnect Architectures: Insights from the HiPChips Workshop at ISCA 2022
Architects' Tech Alliance
Architects' Tech Alliance
Feb 11, 2022 · Industry Insights

FPGA vs ASIC: When to Choose Each for High‑Performance Designs

This article provides a detailed, line‑by‑line comparison of FPGA and ASIC across pre‑fabrication cost, unit cost, time‑to‑market, performance, power consumption, field update capability, density, design flow, verification, upgrade paths, and the role of structured ASICs, helping engineers decide the optimal solution for complex, high‑performance, non‑standard IC designs.

ASICFPGAcost analysis
0 likes · 11 min read
FPGA vs ASIC: When to Choose Each for High‑Performance Designs
Architects' Tech Alliance
Architects' Tech Alliance
Nov 18, 2021 · Fundamentals

Challenges and Future Directions in Computing System Design: Logic, Memory, and Interconnect

The article reviews the accelerating data explosion and its impact on computing hardware, analyzes the limits of traditional scaling in logic, memory, and interconnect, and proposes specialized ICs, design reuse, 3‑D integration, new memory technologies, and optical interconnects as viable paths to sustain performance growth.

computinghardware designinterconnect
0 likes · 30 min read
Challenges and Future Directions in Computing System Design: Logic, Memory, and Interconnect
Architects' Tech Alliance
Architects' Tech Alliance
Oct 16, 2021 · Fundamentals

The New Golden Age of Computer Architecture: Trends, Challenges, and Opportunities

This article reviews the historical evolution of computer architecture, analyzes the end of Dennard scaling and Moore's Law, discusses domain‑specific architectures, open ISAs like RISC‑V, security vulnerabilities, and emerging opportunities such as agile hardware development and specialized accelerators.

Performance ScalingRISC-VSecurity Vulnerabilities
0 likes · 41 min read
The New Golden Age of Computer Architecture: Trends, Challenges, and Opportunities
Architects' Tech Alliance
Architects' Tech Alliance
Nov 13, 2019 · Industry Insights

How SmartNICs Transform Data Center Performance: Types, Benefits, and Design Strategies

The article explains how SmartNICs offload networking, storage, and compute tasks from CPUs to improve server performance and reduce power consumption, outlines three SmartNIC architectures—multicore ASIC, FPGA‑based, and FPGA‑enhanced—and details design methods and functional extensions illustrated with thirteen practical examples.

ASICFPGANetwork Acceleration
0 likes · 14 min read
How SmartNICs Transform Data Center Performance: Types, Benefits, and Design Strategies
Architects' Tech Alliance
Architects' Tech Alliance
Jul 27, 2019 · Fundamentals

A Comprehensive Overview of Chip Design Process and EDA Toolchain

The article provides a detailed, English-language overview of the entire integrated circuit design flow—from architecture and algorithm selection through RTL coding, verification, synthesis, layout, and sign‑off—highlighting the roles, tools, and challenges faced by engineers in modern ASIC and FPGA development.

ASICChip DesignEDA
0 likes · 29 min read
A Comprehensive Overview of Chip Design Process and EDA Toolchain
DataFunTalk
DataFunTalk
Jul 22, 2019 · Artificial Intelligence

Key Hardware Design Considerations for Autonomous Vehicles

The article examines autonomous vehicle hardware, covering aesthetic design, sensor placement for full 360° vision, weather impacts on perception, performance versus power consumption, cooling solutions, and environmental robustness such as vibration, temperature, humidity, salt corrosion, and electromagnetic interference, while highlighting modular sensor modules and innovative concepts like Zoox's direction‑free chassis.

autonomous vehicleshardware designperformance
0 likes · 12 min read
Key Hardware Design Considerations for Autonomous Vehicles
Architects' Tech Alliance
Architects' Tech Alliance
May 20, 2019 · Fundamentals

Comprehensive Overview of FPGA: Introduction, History, Architecture, Development Flow, and Application Scenarios

This article provides a detailed introduction to Field‑Programmable Gate Arrays (FPGA), covering their definition, evolution, major vendors, internal architecture, design and programming workflow, usage in data‑center and telecom, and typical application scenarios such as AI and high‑performance computing.

ASICFPGAdata center acceleration
0 likes · 13 min read
Comprehensive Overview of FPGA: Introduction, History, Architecture, Development Flow, and Application Scenarios
21CTO
21CTO
Aug 26, 2015 · Fundamentals

Why Are CPU Registers Faster Than Memory? Three Key Reasons Explained

Registers outrun main memory because they sit closer to the CPU, employ high‑performance hardware designs, and involve far fewer access steps, a distinction illustrated with examples from iPhone 5s architecture and detailed step‑by‑step memory access processes.

CPU architectureMemory HierarchyRegisters
0 likes · 6 min read
Why Are CPU Registers Faster Than Memory? Three Key Reasons Explained
Art of Distributed System Architecture Design
Art of Distributed System Architecture Design
May 22, 2015 · Industry Insights

How Facebook Cuts Power Use with Cold Storage: Inside Their Low‑Energy Data Center Design

This article examines Facebook's cold storage system, detailing how the company redesigned hardware and software to slash power consumption, improve reliability with Reed‑Solomon coding, mitigate bit‑rot, and balance loads while supporting massive photo archives in energy‑constrained data centers.

FacebookReed-Solomoncold storage
0 likes · 8 min read
How Facebook Cuts Power Use with Cold Storage: Inside Their Low‑Energy Data Center Design