A Comprehensive Overview of Chip Design Process and EDA Toolchain

With the surge of interest in integrated circuits, the author sets out to map the chip design process from an EDA perspective, noting that his familiarity is limited to the digital portion while the system, software, and application layers remain largely unknown.

From a consumer standpoint, a usable system comprises digital ICs, analog ICs, system software, and applications; analog circuits interface with the external world, converting signals to binary for digital processing, then back to analog for output, making the chip the skeleton and software the soul.

Using a mobile baseband chip as an example, the digital design flow begins with extensive protocol documents. Architects decide which protocol parts are implemented in hardware versus software, algorithm engineers study the protocols and select algorithms, chip designers translate algorithms into RTL, verification engineers create test vectors for functional and performance validation, digital implementation engineers synthesize RTL into GDS based on PPA targets, and finally production and testing are outsourced to foundries and third‑party test platforms.

The architect’s decisions influence about 60 % of chip performance; tools such as C/C++, Matlab, and GCC are commonly used for algorithm simulation and verification.

Design engineers rely on a suite of EDA tools: editors (VIM, Emacs), lint/checkers (Spyglass, Jasper), CDC tools (Conformal, GCA), power‑intent checkers (CLP), power analysis tools (Joules, PA), simulators (C, SystemC, ModelSim, VCS), and synthesis tools (Genus, Design Compiler).

Integration engineers connect all IP blocks according to the architecture, ensuring correct inter‑connections without over‑ or under‑linking, typically using simple editors like Emacs due to a lack of dedicated integration tools.

Verification runs in parallel with synthesis, iterating repeatedly. Modern verification methodologies have evolved from OVM to UVM, and from dynamic simulation to static verification, FPGA prototyping, and emulation. Verification engineers must understand both the protocols and the design itself, using languages such as C/C++, SystemVerilog, and tools like dynamic simulators, static checkers, FPGA boards, and emulators (e.g., Cadence Palladium).

FPGA verification is widespread; major vendors include Altera (now Intel) and Xilinx, with tools like Synplify and Quartus supporting synthesis, place‑and‑route, and debugging.

The implementation phase focuses on synthesis, formal verification, low‑power verification, RTL power analysis, and static timing analysis (STA). Advanced synthesis (high‑level synthesis) translates C/C++/SystemC into RTL for compute‑intensive designs. Traditional synthesis converts RTL/VHDL into technology‑mapped netlists, optimizing for capacity, speed, and correlation with place‑and‑route tools such as Genus and Design Compiler.

Design for Test (DFT) inserts scan chains, BIST, boundary‑scan, and generates ATPG patterns; ECO tools (e.g., Cadence Conformal ECO) address late‑stage bug fixes. Layout and routing have become exponentially more complex from 90 nm to 3 nm, with tools like Innovus leading the new era, and AI techniques beginning to assist in power‑optimal routing decisions.

Power sign‑off verifies IR‑drop and electromigration using tools like Voltus and RedHawk, while physical verification checks design rule compliance with tools such as Calibre, PVS, and ICV. The article concludes that despite the dominance of a few EDA vendors, substantial investment in domestic EDA capabilities is essential for a strong national chip industry.

Overall, the article emphasizes that mastering EDA tools and investing in domestic EDA capabilities are crucial for advancing China’s chip industry.