What’s Next for AI Chip Manufacturing? 2025 Roadmap of Process, Packaging, and HBM

Semiconductor Process Evolution

IRDS optimistic forecast predicts rapid evolution of logic device manufacturing over the next five years, with initial 3‑D integration of logic devices expected by 2025. TSMC and Samsung are projected to begin volume production of gate‑all‑around (GAA, also called MBCFET) 2 nm and 3 nm processes around 2025.

TSMC’s roadmap (2023‑2025) is dominated by 3 nm technology; 2 nm is scheduled after 2025. The N3 (3 nm) node entered mass production in 2023, with N3E (enhanced) also launched. In the second half of 2024 TSMC will start N3P production, offering higher speed, lower power, and higher chip density than N3E. The N3X variant, targeted at high‑performance computing, aims for higher clock frequencies and is expected in volume production in 2025. Historical data show that process‑related performance gains for logic devices are projected to be less than 50 %, indicating that future single‑chip compute improvements will rely increasingly on advanced packaging.

Advanced Packaging Evolution

TSMC’s CoWoS (chip‑on‑wafer‑on‑substrate) advanced‑packaging substrate size is measured relative to the reticle area. In 2023 the substrate area is approximately 4 × the reticle; the roadmap projects about 6 × by 2025. For reference, Nvidia’s H100 GPU currently uses a substrate less than 2 × reticle, while AMD’s MI300 series GPUs use substrates around 3.5 × reticle, approaching the limits of the current CoWoS‑L process.

HBM Memory Evolution

High‑bandwidth memory (HBM) capacity is expected to reach 24 GB in 2024 and 36 GB in 2025. HBM4 will introduce two major changes:

Interface width doubles from 1024 bits to 2048 bits, effectively doubling per‑stack bandwidth.

Industry prototypes are stacking the HBM die directly on top of the logic die, reducing interposer length and latency.

These trends continuously increase both bandwidth and the amount of memory that can be accommodated within a single package.

Projection Assumptions

Assumption 1: Each AI‑chip generation maintains roughly the same storage‑compute‑interconnect ratio, delivering 1.5‑2 × performance improvement over the previous generation.

Assumption 2: Process technology evolves gradually and predictably, with no disruptive jumps before 2025.

Under these assumptions, by 2025 the manufacturing node is expected to remain at 3 nm, with process‑related performance gains limited to less than 50 %. Advanced packaging is projected to achieve substrate areas about 6 × reticle, and HBM capacity is projected to grow to 24 GB (2024) and 36 GB (2025).

Source: https://www.chaspark.com/#/hotspots/950120945305616384