The new consumer‑grade robot from VeilBlue delivers a thousand‑fold compute boost over previous models, matching Nvidia's Jetson AGX Thor while costing only one‑tenth, thanks to a six‑chip heterogeneous edge cluster, human‑surpassing perception, and safety‑first design validated in real homes.
The article analyzes the severe inference bottlenecks of large language models, CNNs, and recommendation systems and presents a suite of research‑driven accelerations—including token‑level pipeline parallelism (HPipe), KV‑cache clustering (ClusterAttn), quantization (QoKV), heterogeneous edge frameworks (DeepZoning, PICO), delay‑aware edge‑cloud scheduling (DECC), and operator choreography (RACE)—validated on real‑world industrial workloads.
The article argues that traditional storage‑centric computer science curricula are becoming obsolete as AI‑driven, compute‑centric paradigms dominate hardware, data‑center operations, and software ecosystems, urging universities and students to rapidly adopt new teaching focus and skills.
This article explains the fundamentals of high‑performance computing (HPC), covering serial and parallel processing, the roles of CPUs and GPUs, system architectures, FLOPS metrics, current supercomputer capabilities, and the scale needed to reach the next exa‑FLOPS era.
This article explains why migrating AI applications from Nvidia GPUs to domestic graphics cards is urgent, outlines the technical challenges, and introduces JoyScale’s zero‑perception migration stack that enables end‑to‑end hardware, software, and model adaptation for reliable, high‑performance AI deployment.
This article explains why migrating AI applications from Nvidia GPUs to domestic Chinese accelerators is urgent, outlines the technical challenges, and presents JD Cloud's JoyScale zero‑perception migration stack with hardware, software, model, and inference optimizations for real‑world scenarios.
NVLink Fusion, unveiled at Computex 2025, extends NVIDIA’s NVLink technology to enable high‑bandwidth, low‑latency connections between CPUs and GPUs or third‑party accelerators, offering up to 900 GB/s bandwidth, flexible heterogeneous configurations, ecosystem expansion, performance gains for AI training and inference, and potential cost reductions.
This article provides an in‑depth technical analysis of Huawei’s Ascend AI accelerator architecture, detailing its heterogeneous compute units, memory hierarchy, task scheduling, programming model, compiler optimizations, and the capabilities of the Ascend 310 and 910 chips, while also discussing future challenges and market competition.
The article details Baidu Baige 4.0’s four‑layer AI infrastructure—hardware, cluster components, training‑inference acceleration, and platform tools—highlighting its heterogeneous computing, high‑performance networking, fault‑tolerant communication library, and optimizations that boost large‑model training and inference efficiency.
The article reviews NVIDIA's newly released H20 AI accelerator for China, compares its performance and pricing with domestic chips, outlines the expanding Chinese AI chip ecosystem—including Huawei, Cambricon, HaiGuang, Alibaba, ByteDance, and Baidu—while highlighting market size growth, multi‑chip heterogeneity strategies, and the strong demand forecast through 2024.
The article examines how the surge of generative AI (AIGC) is fueling rapid growth in AI server demand, detailing the emerging AIGC ecosystem, server hardware composition, model scaling, heterogeneous computing, training vs. inference workloads, market size forecasts, and the competitive landscape of AI server manufacturers.
With AI training demands outgrowing single‑chip GPU clusters, this article explains how to construct and speed up heterogeneous AI clusters—combining GPUs, Kunlun, and Ascend chips—by addressing interconnect, distributed parallel strategies, and specialized acceleration suites to achieve high MFU and efficient large‑model training.
The article analyzes how the surge in AIGC and large language models is reshaping the AI server market, detailing hardware composition, the rise of heterogeneous computing, GPU advantages, demand calculations for models like GPT‑3, and the competitive landscape driving rapid industry growth.
Senior big data engineer Zhu Yaogai from HuoLala shares the team’s three‑year journey, detailing background challenges, the construction of a multi‑layer big‑data infrastructure, solutions for cost efficiency, operational automation, heterogeneous computing, and future plans, illustrating how high cost‑effectiveness, operational efficiency, and analytical performance drive their evolution.
The article details JD Retail Advertising's three‑stage evolution of its online model system—deep‑learning era, large‑model era, and power‑collaboration era—highlighting heterogeneous computing optimizations, platform and system capabilities, distributed graph computing, online learning, and dynamic power allocation to dramatically improve algorithm iteration speed and model performance.
The article analyzes the shift from x86 to ARM in server hardware, compares CISC and RISC instruction sets, reviews domestic Chinese CPU projects, examines GPU/NPU/FPGA accelerators, and proposes concrete ARM instruction‑set, compiler, and operating‑system standards for the telecom industry.
An in‑depth overview of AI server components, market growth, AIGC‑driven demand, heterogeneous computing architectures, major vendors, and future trends, highlighting hardware composition, cost breakdown, competitive rankings, and the impact of GPU, CPU, and emerging AI accelerators on the industry.
In a keynote at Baidu Cloud Intelligence Conference, Baidu's VP Hou Zhenyu explains how the rise of large AI models is reshaping cloud infrastructure, spawning new architectures, services, and computing paradigms that converge mobile, deep learning, and cloud into an AI‑native era.
The article explains the various AI‑capable chips such as CPUs, GPUs, FPGAs, NPUs, and TPUs, compares their performance and efficiency, describes heterogeneous CPU+xPU solutions, and provides market share data while highlighting the growing adoption of specialized AI accelerators.
The article provides a comprehensive analysis of the AI server market, detailing server hardware components, cost distribution, logical architecture, firmware, rapid market growth, competitive landscape, AI-driven heterogeneous computing, and future industry trends, while highlighting key vendors and deployment configurations.
Tencent Cloud’s Hybrid vCPU research, presented at KVM Forum 2023, outlines a three‑stage roadmap from homogeneous cores to mixed x86, ARM, and RISC‑V CPUs, detailing how virtualizing heterogeneous topologies, frequencies, caches, and PMU features can boost VM performance, security, live‑migration flexibility, and data‑center utilization.
This article presents a comprehensive overview of PaddlePaddle's automatic parallel design for heterogeneous scenarios, covering background motivation, architectural principles, key implementation details, practical usage interfaces, and future outlook, while illustrating concepts with detailed diagrams and examples.
At the GTC conference, the talk presents Alibaba Cloud’s heterogeneous computing platform and introduces the Open Deep Learning API (ODLA), then details how CUTLASS‑based operator fusion dramatically accelerates attention and MLP layers in large‑scale recommendation models, achieving multi‑fold performance gains in production.
Intel’s recent announcements, featuring Linus Torvalds, the open‑source OneAPI ecosystem, SYCL‑based cross‑architecture tools, and the new Intel Developer Cloud, illustrate how the company is driving a unified, hardware‑agnostic platform for AI, accelerated computing, and secure cloud workloads.
The article explains how massive parallel pixel calculations demand GPUs, whose high cost and inflexibility are solved by Tencent Cloud’s elastic, virtualized GPU services—including vGPU, qGPU, TACO abstraction, and spot instances—delivering up to 16 EFLOPS for AI, scientific, graphics, and video workloads.
This article surveys the rapid growth of data‑center capacity, the rise of AI and big‑data workloads, and how emerging accelerators such as GPUs, DPUs, SmartNICs and heterogeneous CPU designs from Intel, AMD, Arm and Apple are reshaping server hardware and driving a new wave of performance and efficiency competition.
The article surveys GPU container virtualization for AI heterogeneous computing, detailing utilization challenges, historical architectures, various virtualization methods, Baidu's dual-engine user- and kernel-space design with isolation and scheduling features, performance benefits, best‑practice scenarios, and deployment guidance, concluding with a technical Q&A.
This article explains the fundamentals of high‑performance computing, covering serial and parallel processing, heterogeneous CPU‑GPU architectures, FLOPS measurement levels, key terminology, and why HPC is essential for scientific and engineering simulations, while also noting market reports and resource links.
This article thoroughly explains libunifex’s sender/receiver model for C++ asynchronous programming, covering its design goals, module structure, pipeline composition, key functions like schedule, then, sync_wait, and the connect/start mechanisms, while demonstrating practical examples and integration with C++20 coroutines and cancellation support.
The article analyzes how the slowdown of Moore's Law drives a shift from general‑purpose CPUs to specialized XPU, FPGA, DSA and ASIC designs, highlights heterogeneous chiplet integration, edge‑server growth, and the emerging importance of software, algorithms and architecture in boosting performance and efficiency.
This article introduces the fundamentals of heterogeneous computing on mobile GPUs, explains OpenCL concepts and its programming model, and provides a step‑by‑step example of adding two arrays with complete OpenCL code for Android devices.
As mobile CPUs plateau, developers increasingly use OpenCL to harness Android GPUs like Qualcomm Adreno and Huawei Mali for heterogeneous computing, leveraging its platform, execution, and memory models to write portable kernels—illustrated by a simple array‑addition example that demonstrates device initialization, kernel creation, buffer management, and parallel execution.
The report analyzes how the rapid growth of cloud computing previously drove server demand, and how the emergence of 5G‑enabled edge computing is now reshaping server architectures, hardware needs, deployment models, and operational challenges, forecasting a significant increase in server volume for edge scenarios.
The article summarizes Dr. Tang Shan's presentation on AI domain‑specific architectures, covering their background, the explosion of diverse AI hardware designs, and the significant software‑stack challenges that arise from fragmented tools and the need for full‑stack solutions.
The article analyzes how compute has evolved from performance‑driven Moore’s‑law scaling to a comprehensive innovation era driven by cloud democratization, heterogeneous accelerators, edge and memory‑centric architectures, outlining IDC’s ten future‑compute characteristics such as flexible deployment, AI‑enabled operations, multi‑cloud, security and next‑gen interconnects.
Baidu’s elastic nearline computing architecture inserts an asynchronous, resource‑adaptive layer between online and offline processing, dynamically harvesting idle CPU, GPU and Kunlun XPU capacity to pre‑compute complex recommendation and search policies, enabling peak‑shifting, valley‑filling, higher timeliness and significant business growth at low cost.
The article examines the rapid growth of data‑center workloads, explains why heterogeneous accelerators such as CPUs, GPUs, FPGAs and ASICs are needed, outlines evaluation standards, compares their compute performance and power efficiency, and discusses practical deployment cases and future trends.
The article explains how the fourth paradigm's distributed machine learning framework GDBT tackles the massive data, high‑dimensional features, and real‑time requirements of modern recommendation systems by leveraging heterogeneous computing, parameter servers, RDMA networking, and optimized workloads.
The article provides a comprehensive overview of heterogeneous computing, detailing its definition, real‑world system examples, performance advantages, key programming frameworks such as OpenCL and CUDA, industry trends like SOC integration, and a comparative analysis of CPUs, GPUs, FPGAs and ASICs.
This article explains how Alibaba Cloud builds a high‑performance AI infrastructure by combining advanced hardware such as Shenlong servers, GPUs, FPGAs, NPUs, and custom interconnects like RDMA, together with virtualization, FPGA‑as‑a‑Service, AIACC, and resource‑pooling technologies to deliver scalable, cost‑effective AI services.
This article analyzes how system architects can select the optimal heterogeneous compute cores—CPU, GPU, FPGA, ASIC, VPU, or TPU—for edge AI deployments, weighing performance, size, weight, power, and cost to maximize inference efficiency and security.
This article explains heterogeneous computing and compares major processing units—CPU, GPU, FPGA, ASIC, and NPU—highlighting their architectures, strengths, and typical use cases, especially in deep‑learning and AI workloads.
The article examines the rapid growth of information system energy consumption, defines green computing, outlines its research focus—especially on data centers, cloud computing and servers—and analyzes a range of energy‑saving technologies such as DVFS, heterogeneous computing, liquid cooling, rack‑level servers, advanced power supply, backplane cooling and fluorocarbon pump AC systems.
The article explains why 5G forces multimedia standardization, outlines the challenges of emerging formats like 8K, details the VVC (H.266) compression breakthrough, and describes Tencent's role in shaping future heterogeneous‑computing‑based multimedia architectures for cloud gaming and beyond.
The article explains how heterogeneous parallel computing—distributing tasks across CPUs, GPUs, FPGAs and other accelerators—has become essential after Moore’s law plateau, detailing its principles, hardware and software perspectives, classification of architectures, processing stages, user‑guided versus compiler‑guided methods, and its relevance to AI, cloud and industry workloads.
The article explains how heterogeneous parallel computing—leveraging CPUs, GPUs, FPGAs and other specialized units—addresses the performance limits of traditional serial programming by distributing tasks across diverse hardware, detailing its concepts, architectures, development models, and relevance to AI and cloud workloads.
At the 2017 International Workshop on Mathematical Issues in Information Sciences, Alibaba researcher Zhang Weifeng presented a talk on leveraging heterogeneous computing—re‑architected processors, memory‑wall mitigation, and integrated software‑hardware optimization—to dramatically improve machine‑learning performance, highlighting the growing importance of compute resources alongside algorithmic advances.
The article explains why general‑purpose CPUs can no longer meet deep‑learning demands due to intrinsic scaling limits and memory‑bandwidth bottlenecks, and surveys how heterogeneous accelerators—GPUs, FPGAs, ASICs and emerging AI processors with high‑bandwidth memory—provide specialized, high‑parallelism, power‑efficient solutions for both cloud and edge workloads.
The article analyzes the limitations of general‑purpose CPUs for deep‑learning workloads, explains how semiconductor scaling and memory‑bandwidth constraints drive the shift toward specialized heterogeneous processors such as GPUs, FPGAs, and ASICs, and discusses the design trade‑offs of embedded versus cloud AI accelerators.
