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Unified memory

10 articles · Page 1 of 1
Architects' Tech Alliance
Architects' Tech Alliance
Jul 20, 2026 · Artificial Intelligence

Supernode Architecture Explained: Definitions, Core Features, and Practical Use Cases

The whitepaper defines supernodes as high‑speed, tightly‑connected compute systems with unified memory addressing, microsecond‑level latency and terabyte‑per‑second bandwidth, outlines their physical, transaction, function and topology layers, demonstrates AI training and inference gains such as 80% communication reduction and 98.4% cluster scaling efficiency, and discusses industry impact, future scaling, standardization and green energy trends.

AI infrastructureHardware‑software co‑designLarge model training
0 likes · 8 min read
Supernode Architecture Explained: Definitions, Core Features, and Practical Use Cases
Lao Guo's Learning Space
Lao Guo's Learning Space
Jun 3, 2026 · Industry Insights

Can Apple’s M5 Ultra Still Compete After NVIDIA’s RTX Spark Launch?

The RTX Spark desktop processor delivers 1 PFLOP of AI compute—about 14 times the M5 Ultra—while the M5 Ultra retains a three‑times higher memory bandwidth and twice the memory capacity, making it superior for certain inference workloads; the article breaks down specs, benchmarks, ecosystem differences, pricing and market positioning to show how each platform fits distinct AI use cases.

AI computeApple M5 UltraCUDA
0 likes · 12 min read
Can Apple’s M5 Ultra Still Compete After NVIDIA’s RTX Spark Launch?
Architects' Tech Alliance
Architects' Tech Alliance
Mar 7, 2024 · Industry Insights

How Nvidia GH200 and AMD MI300A Are Redefining CPU‑GPU Memory Integration

The article examines Nvidia’s GH200 and AMD’s MI300A processors, highlighting their unified memory domains that eliminate PCIe bottlenecks, detailing benchmark results, power‑measurement challenges, and the broader industry shift toward integrated CPU‑GPU architectures for high‑performance and generative‑AI workloads.

AMD MI300ACPU‑GPU IntegrationHPC
0 likes · 11 min read
How Nvidia GH200 and AMD MI300A Are Redefining CPU‑GPU Memory Integration
Big Data Technology & Architecture
Big Data Technology & Architecture
Dec 6, 2021 · Big Data

Understanding Spark’s Memory Model: Unified Memory Management, On‑Heap and Off‑Heap Memory, and Configuration

This article explains Spark’s unified memory management model, detailing the division between on‑heap and off‑heap memory, the roles of execution, storage, user, and reserved memory, configuration parameters, dynamic allocation, and how these concepts affect performance and resource utilization.

Execution MemoryMemory ManagementOff‑Heap
0 likes · 17 min read
Understanding Spark’s Memory Model: Unified Memory Management, On‑Heap and Off‑Heap Memory, and Configuration
Big Data Technology & Architecture
Big Data Technology & Architecture
Jul 5, 2020 · Big Data

Understanding Spark Memory Management: On‑heap, Off‑heap, and Unified Memory

This article provides a comprehensive overview of Spark's memory management, covering executor memory architecture, the differences between on‑heap and off‑heap memory, static versus unified memory managers, storage and execution memory handling, and practical guidelines for optimizing Spark applications.

Big DataExecutorMemory Management
0 likes · 21 min read
Understanding Spark Memory Management: On‑heap, Off‑heap, and Unified Memory
Big Data Technology & Architecture
Big Data Technology & Architecture
Jun 1, 2019 · Big Data

Understanding Spark Executor Memory Management: On‑Heap, Off‑Heap, and Unified Memory

This article explains Spark's executor memory architecture, covering on‑heap and off‑heap memory planning, static and unified memory managers, storage and execution memory allocation, RDD persistence, eviction policies, and shuffle memory usage, providing practical guidance for performance tuning.

Big DataExecutorMemory Management
0 likes · 23 min read
Understanding Spark Executor Memory Management: On‑Heap, Off‑Heap, and Unified Memory