CISC vs RISC: How Complex and Simple Instruction Sets Compete

1. What is an instruction set?

An instruction is the basic operation a CPU performs, such as addition, jump, or memory access. The instruction set is the complete collection of instructions a CPU supports, essentially the processor’s "martial arts manual."

指令 = CPU执行的基本操作  比如：
- 加法指令：把两个数相加
- 跳转指令：跳到某个位置继续执行
- 读写内存指令：存取数据
指令集 = CPU支持的所有指令的集合 = CPU的"武功秘籍"

2. CISC: Complex Instruction Set

Full name

Complex Instruction Set Computer (CISC)

Representative implementations

- x86/x64 (Intel, AMD)
- IA-64 (Itanium)
- Evolution: 8086 → 80286 → 80386 → Pentium → …

Core idea

"用一条指令完成复杂任务"
Example: string copy
CISC: MOVS (single instruction copies a string)
RISC: needs a loop of LOAD/STORE instructions

Characteristics

Instruction traits:
- Variable length (1–15 bytes)
- Variable execution time
- Many addressing modes
- Few registers (8–16 general‑purpose)
Example x86 instructions:
MUL BX   ; AX = AX * BX
REP MOVSB ; copy string in one instruction

Why CISC has complex instructions?

Historical background (1970s): memory was expensive, so complex instructions aimed to reduce instruction count and memory usage, and simplify programming. In practice, decoding complex instructions is slow, consumes many transistors, and yields limited performance gains.

3. RISC: Reduced Instruction Set

Full name

Reduced Instruction Set Computer (RISC)

Representative implementations

- ARM (dominant RISC)
- MIPS (academic example)
- RISC‑V (open‑source newcomer)
- PowerPC (IBM’s RISC)

Core idea

"Simple instructions are fast; many of them can be combined to perform complex work"
Principles:
1. Fixed instruction length (4 bytes)
2. Fixed execution time (usually 1 cycle)
3. Simple addressing modes
4. Many registers (16–32 general‑purpose)

Characteristics

Instruction traits:
- Fixed length
- Only LOAD/STORE can access memory
- Many registers
- Small instruction set (tens to a few hundred)
Example ARM instructions:
ADD R0, R1, R2   ; R0 = R1 + R2
LDR R0, [R1]     ; load from memory
STR R0, [R1]     ; store to memory

4. Full comparison

Instruction count: CISC – many (hundreds); RISC – few (tens)

Instruction length: CISC – variable; RISC – fixed

Execution cycles: CISC – variable; RISC – fixed

Registers: CISC – few; RISC – many

Memory access: CISC – flexible; RISC – LOAD/STORE only

Decoding difficulty: CISC – complex; RISC – simple

Power consumption: CISC – higher; RISC – lower

Cost: CISC – higher; RISC – lower

Representative architecture: CISC – x86; RISC – ARM

5. Why ARM is so successful?

ARM = Advanced RISC Machine
Success factors:
1. Low power → preferred for mobile devices
2. Licensing model → used by Apple, Samsung, Qualcomm, etc.
3. Simple design → fewer transistors, low heat
4. Pipeline‑friendly → high‑frequency operation
Market share:
- >95 % of smartphone processors are ARM
- Dominates embedded market
- Apple M‑series ARM chips are challenging x86 in PCs

6. Modern processors “fusion”

In reality the line between CISC and RISC is blurring.

Intel’s approach

x86 processors internally:
- External: compatible x86 instructions (CISC)
- Internal: translate CISC to micro‑operations (RISC‑like)
- Execution: RISC‑style pipeline
This “decode‑and‑execute” technique started with Pentium Pro (1995), the first CPU with a RISC core behind a CISC façade.

ARM’s evolution

Early ARM: pure RISC
Modern ARM: adds complex instruction accelerators such as NEON SIMD, hardware floating‑point, and prefetch optimisations – moving toward “complex” capabilities.

Apple M1 case

M1 = ARM architecture (RISC) but outperforms x86 because of:
1. Large + many cores
2. Unified memory architecture
3. Advanced micro‑architecture design
4. 5 nm process
Illustrates that the instruction set is only a starting point; micro‑architecture matters most.

7. Pipeline: RISC’s accelerator

RISC’s speed comes from pipelining.

Five‑stage pipeline: IF → ID → EX → MEM → WB (fetch, decode, execute, memory, write‑back)
At any moment five instructions are in different stages, giving up to 5× throughput.
RISC suits pipelines because:
- Fixed instruction length → simple decode
- Fixed execution cycle → easy scheduling
- Many registers → fewer data dependencies

8. RISC‑V: Open‑source new force

RISC‑V:
- Born 2010 at UC Berkeley
- Fully open and free, no licensing fees
- Simple ISA
China’s enthusiasm:
- Not subject to US export controls
- Enables independent design
- Fits IoT chips
Notable shipments: Alibaba’s Pingtouge >30 billion chips; Huawei, Zhaoyi also have RISC‑V product lines.

9. Summary

CISC (x86):
- Strong compatibility, rich ecosystem
- Higher power, suited for desktop/server
- Intel/AMD dominate
RISC (ARM):
- Low power, ideal for mobile/embedded
- Open licensing, high flexibility
- Expanding into PC/server
Future trend:
- Fusion: RISC‑style cores with CISC compatibility, and CISC learning RISC design
- ARM challenging x86 in PCs/servers
- RISC‑V open‑source rise

Instruction sets are just the starting point; the real battle is in micro‑architecture!

Key takeaways:

CISC instructions are complex and numerous; x86 is the flagship.

RISC instructions are simple and few; ARM is the flagship.

RISC fits pipelines, offers low power.

CISC offers better compatibility and a mature ecosystem.

Modern CPUs are converging toward a hybrid design.