Understanding GPUs, AI Accelerators, and Market Trends

GPU was initially used in PCs and mobile devices for graphics processing and later integrated with CPUs as integrated graphics; in 2007 NVIDIA introduced the first discrete GPU, acting as a co‑processor for PCs and servers, composed of a core chip, memory, and interface circuitry.

Discrete GPUs connect to CPUs via the PCIe bus, making PCIe bandwidth a key factor; NVIDIA’s NVLink technology replaces traditional PCIe for GPU‑to‑GPU interconnect, claiming up to a five‑fold performance increase.

Although AI performance still has room for growth and many servers have unused GPU capacity, short‑term upgrades from PCIe 3.0 to 4.0 and 5.0 will have limited impact on GPUs, while manufacturers continue to advance product processes. According to AIBResearch, NVIDIA holds nearly 80% of the discrete GPU market, and its Ampere A100 7nm product is already in production.

Market data shows a three‑way split among NVIDIA, AMD, and Intel: overall GPU market shares are roughly 63% Intel, 19% AMD, and 18% NVIDIA. Intel and AMD dominate the integrated‑GPU segment, while in the x86 CPU market Intel holds 84% and AMD 16%. In the discrete GPU market, NVIDIA is the leader with about 70% share; in Q4 2019 NVIDIA held 81% versus AMD’s 19%. For HPC and AI workloads, NVIDIA offers the Tesla series (V100, P100, K40/K80, M40/M60, etc.), where K‑series chips suit high‑precision computing and M‑series target deep learning.

In March 2019 NVIDIA announced a $4.9 billion acquisition of Mellanox, finalized by April 2020, marking NVIDIA’s largest purchase. Mellanox provides end‑to‑end connectivity solutions for HPC, cloud, data‑center, and enterprise markets, including Smart NICs, switch ASICs, and high‑speed interconnects.

AI chips are widely used in smart cameras, autonomous driving, and other domains. The three pillars of AI are data, compute, and algorithms; a typical AI deployment combines CPUs with accelerator chips (GPU, FPGA, ASIC) to boost compute and enable algorithm development. GPU, FPGA (Field‑Programmable Gate Array), and ASIC (Application‑Specific Integrated Circuit) are the main accelerator types.

CPU excels at logical control and serial computation but lacks the massive parallelism of GPUs, which consist of thousands of small, efficient cores and can replace hundreds of general‑purpose CPUs for HPC and AI tasks. FPGA offers semi‑custom flexibility and high integration at the cost of lower volume production and higher per‑unit cost, suitable for rapidly changing algorithms or niche markets. ASIC provides the highest specialization and economies of scale for high‑demand applications, though development is lengthy and complex; Google’s TPU (Tensor Processing Unit) is a notable ASIC designed for machine‑learning workloads.

Training and inference are the two primary cloud‑AI processes. Training, which generates algorithms, requires extensive data computation, with GPUs accounting for roughly 64% of the market, FPGA 22%, and ASIC 14%. Inference, which applies trained models, sees GPUs at about 42%, FPGA 34%, and ASIC 24%. AI chip usage spans cloud (servers), edge, and endpoint scenarios, each with distinct requirements. The cloud AI‑chip market is projected to reach $20 billion in 2023.

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