Jul 18, 2026 · Fundamentals

Why Most Spinlock Authors Misinterpret the PAUSE Instruction

The article explains that the PAUSE (F3 90) instruction does far more than save power or yield to hyper‑threads—it controls speculation depth, avoids memory‑ordering penalties on lock release, and its behavior differs on x86 versus ARM, with misuse causing severe performance regressions in spin‑wait loops.

ARMSMTmemory ordering

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Why Most Spinlock Authors Misinterpret the PAUSE Instruction

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May 31, 2020 · Databases

Why Intel’s PAUSE Instruction Slows MySQL on Skylake CPUs and How to Fix It

This article examines how the increased latency of Intel's PAUSE instruction on Skylake CPUs creates a performance bottleneck for MySQL, details the profiling steps that identified ut_delay as the hotspot, and presents a series of optimizations—including spin‑wait parameter tuning and a MySQL 8.0 patch—that restore throughput on affected hardware.

CPU performanceMySQLpause instruction

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Why Intel’s PAUSE Instruction Slows MySQL on Skylake CPUs and How to Fix It