Why Integrated Chiplet Architecture Is Shaping the Future of Semiconductors

According to the "Integrated Chip and Chiplet Technology Whitepaper," the development of integrated chips and chiplets is crucial for the next generation of semiconductor performance.

What Is an Integrated Chip?

An integrated chip first manufactures functional chiplets (small chips with specific functions such as CPUs, memory, GPUs, encryption engines, or network interfaces) and then assembles these chiplets into a full chip using semiconductor integration techniques. The silicon interposer, placed between chiplets and the substrate, provides high‑density interconnects, through‑silicon vias (TSVs), micro‑bumps, and can embed passive components (capacitors, inductors) and active devices (transistors).

Historical Background

The idea originated in 2010 when Dr. Jiang Shangyi of TSMC proposed "advanced packaging" to connect multiple chips via interconnect technology, addressing the area limit of single‑chip manufacturing and board‑level bandwidth constraints. Later, Dr. Sehat Sutrardja (then president of US‑based Meiman Electronics) incorporated modular design concepts.

By 2022, scholars such as Academics Sun Ninghui, Liu Ming, and Jiang Shangyi refined the underlying technologies and introduced the term "Integrated Chips" to replace "advanced packaging" and "chiplet," emphasizing broader implications in architecture, design methodology, theory, and materials.

Three Main Performance‑Boosting Paths

Path 1 – Scaling (Moore’s Law) : Continuously shrinking transistor dimensions to increase density and performance. While this drove exponential gains for decades, sub‑5 nm processes approach physical limits, leading to power, cost, and yield challenges (power wall, storage wall, area wall).

Path 2 – New Device Materials and Principles : Developing novel devices such as FeRAM, RRAM, MRAM, PCM, FeFET, and exploring wide‑bandgap semiconductors, 2‑D materials, and carbon nanotubes. These aim to surpass traditional CMOS performance/energy efficiency but typically have long research‑to‑market cycles.

Path 3 – Chiplet Integration (2.5D/3D) : Breaking the "area wall" by assembling multiple chiplets on a silicon interposer or through‑silicon‑via stack. This approach overcomes lithography size limits and yield loss associated with large monolithic dies. It enables a performance jump equivalent to advancing 1–2 process nodes without requiring next‑generation EUV lithography.

System‑Engineering Design Flow

Integrated‑chip design follows a top‑down methodology: decompose the target application into standard chiplet building blocks, combine these blocks according to the required architecture, and integrate them on an interposer or 3D stack. This "decompose‑combine‑integrate" flow separates chiplet fabrication from system integration.

Early Prototypes and Industry Adoption

The first integrated‑chip prototype was the TSMC‑Xilinx V7200T FPGA, which combined four large FPGA chiplets on a silicon interposer, forming a system with over 2 000 programmable logic gates. This led to the CoWoS (Chip‑on‑Wafer‑on‑Substrate) process, now widely used in high‑performance processors.

Notable products using CoWoS include NVIDIA’s GP100 GPU (GPU chiplet + multiple HBM chiplets) and Huawei’s Ascend 910 AI processor (three chiplet types, six chiplets total). Both demonstrate massive bandwidth gains by integrating compute and memory on a single package.

Recent Advances in 3D Integration

With mature TSV and copper‑copper bonding technologies, 3D integration has become a key trend. AMD and Intel have built high‑performance super‑computing processors using 3D chiplet stacks. Tesla’s DOJO AI training chip employs a fan‑out RDL substrate of 20 000 mm², integrating 25 D1 multi‑core chiplets and photonic communication chiplets.

Domestic Progress in China

Chinese research institutions have made significant strides: the Institute of Computing Technology (CAS) and Zhejiang Lab co‑developed the “Zhejiang Large Chip No. 1,” integrating 16 chiplets each containing 16 CPU cores. Ongoing work on “Zhejiang Large Chip No. 2” aims to further increase integration density and performance.

Fudan University’s Integrated Chip and System National Key Lab demonstrated a 2.5D compute‑in‑memory chip using fan‑out packaging, achieving linear scaling of compute and storage with chiplet count. Alibaba‑DAMO Academy and Unigroup collaborated on a 3D hybrid‑bonded AI accelerator with DRAM stacking. Huawei’s HiSilicon also delivered the Ascend 910 AI processor using similar integration techniques.

Standardization Efforts

Because each chiplet may be designed by a different team, interface standardization is critical. In March 2022, the Universal Chiplet Interconnect Express (UCIe) consortium was founded, led by Intel, to define interoperable chiplet interconnect standards.

Overall, integrated‑chip and chiplet technologies provide a viable path to continue semiconductor performance growth beyond the limits of traditional scaling, combining advances in device physics, packaging, and system architecture.