This article explains a three‑step method—using top to locate the CPU‑hungry Java process, identifying the offending thread, and printing its stack with jstack—to pinpoint and resolve excessive CPU consumption in a Java application running on Linux.
When a computer has no active user tasks, the CPU appears idle but actually runs a special system idle process that repeatedly executes the privileged halt instruction, allowing the processor to enter low‑power states while the operating system manages process queues and scheduling.
When a production container suddenly hit over 90% CPU and excessive JVM garbage collection, the author walks through entering the pod, using top and top‑H to locate the offending thread, extracting its stack with jstack, downloading the data via a simple HTTP server, and ultimately discovering an Excel export routine that caused massive object allocation, fixing the code and restoring stability.
The article provides a comprehensive overview of CPU architecture, covering the distinction between x86 and non‑x86 processors, packaging types, internal components such as the IHS, TIM, die and interposer, the execution pipeline of a Core i7, cache hierarchy, performance metrics, and common cache replacement algorithms.
The 2023 Chinese server CPU industry report details the sector’s rapid growth, classification by instruction set architectures, market characteristics, supply chain analysis, size fluctuations, future forecasts, and competitive dynamics among domestic and foreign manufacturers.
The newly released Loongson 3A6000 processor, built on the domestically designed LoongArch instruction set, delivers performance comparable to Intel's 10th‑gen i3‑10100F, features four high‑performance cores, advanced vector extensions, DDR4‑3200 memory support, and a secure trusted module, marking a major milestone for China's independent CPU development.
The article explains CPU overclocking, covering its feasibility, required high‑quality motherboard, memory and cooling, the relationship between external frequency, multiplier and core speed, and the potential hazards such as increased heat, system instability, reduced component lifespan, and voltage considerations.
The team traced read‑request timeouts to a single overloaded Elasticsearch node where an excessively high node_concurrent_recoveries setting caused many simultaneous shard recoveries and disk‑watermark‑driven relocations, and resolved the issue by lowering concurrent recoveries, enabling adaptive replica selection, and adjusting allocation settings.
The article outlines the major milestones in CPU development—including shrinking process nodes, increasing integration of components, evolving memory controller standards, the progression of PCIe generations, and micro‑architectural enhancements such as larger caches and hybrid core designs—providing a concise historical overview for readers.
This article walks through a real‑world investigation of a pod whose CPU spiked to over 90%, detailing how abnormal JVM garbage‑collection patterns were identified, traced to a specific Java thread, and resolved by fixing an inefficient Excel export routine.
This article explains the fundamental principles of computer operation, covering the von Neumann model, CPU and RAM interaction, instruction sets, memory hierarchy, caches, endianness, compilers, operating systems, and performance optimizations, while illustrating each concept with diagrams and code examples.
This article traces the evolution of CPUs by examining process node reductions, increasing integration of components, memory controller upgrades, PCIe advancements, and microarchitectural innovations that together shape modern processor performance and efficiency.
This article details how Didi identified excessive CPU consumption by ClickHouse's BgMoveProcPool threads, traced the root cause to unnecessary part‑move checks, introduced a simple early‑exit guard in selectPartsForMove, and achieved a dramatic reduction in CPU load while contributing the fix upstream.
This article provides a comprehensive overview of CPU fundamentals, covering core concepts such as clock speed, external frequency, front‑side bus, multiplier, bit and word length, cache hierarchy, instruction sets, voltage levels, manufacturing processes, pipelines, superscalar execution, SMP, multicore designs, multithreading, hyper‑threading, and NUMA technology.
A Java ToB system struggled to meet a 500 requests‑per‑second target, revealing hidden bottlenecks such as slow SQL, excessive logging, thread‑pool misconfiguration, high CPU usage from Spring bean creation, and improper Redis usage, which were systematically identified and mitigated.
This article explains the structure and evolution of modern CPUs, covering the core (die), substrate, filler material, packaging technologies, and the various interface types that connect the processor to the motherboard, while highlighting current trends such as integration of GPU cores and advanced manufacturing processes.
This article explains Intel's CPU naming conventions, generation identifiers, SKU and suffix meanings, details the evolution of Intel processor generations from Haswell to Raptor Lake Refresh, and examines the internal microarchitecture of a Kaby Lake i5‑7200U, including its die layout and core components.
This article explains Intel's CPU naming conventions, the meaning of each part of a processor model string, the evolution of CPU generations from Haswell to Raptor Lake Refresh, and the internal micro‑architecture of a Kaby Lake i5‑7200U, illustrated with die diagrams and code examples.
The article details a step‑by‑step investigation of a Java Spring backend that initially achieved only 50 req/s under load, identifies bottlenecks such as slow SQL, excessive logging, thread‑pool misconfiguration and costly Spring bean creation, and demonstrates how targeted optimizations roughly doubled throughput while reducing response times.
This article explains how CPU core count, clock speed, and cache, as well as GPU shader count, frequency, memory bandwidth, and graphics‑card memory size and interface affect performance, and shows 2023 desktop and laptop performance ladder charts to help users compare and choose the right hardware.
According to Reuters, Nvidia and AMD are designing Arm‑based processors for Windows PCs that could be ready by 2025, while Microsoft continues its partnership with Qualcomm on Arm Windows 11 and rumors suggest Microsoft may also develop its own Arm server chips.
This article explains the fundamental principles of how computers operate, covering the basic architecture of CPUs and memory, the role of buses and registers, instruction sets, compiler translation, cache hierarchies, storage layers, and the impact of 32‑bit versus 64‑bit designs.
This article provides a concise technical overview of server hardware, covering CPU architecture and platform options, GPU evolution and key specifications, and DDR4 memory compatibility rules, helping readers understand the essential components for building or upgrading a server.
High Bandwidth Memory (HBM), introduced in 2014 using TSV stacking, has evolved through HBM2, HBM2e, and HBM3 standards and is now integrated into CPUs, GPUs, and accelerators from AMD, NVIDIA, Intel, and others, with advanced interconnects like CoWoS, EMIB, and Foveros enabling high‑capacity, high‑bandwidth packaging.
The article provides a comprehensive overview of China's six leading domestic server CPU manufacturers—Zhaoxin, HaiGuang, FeiTeng, KunPeng, Loongson, and ShenWei—examining their instruction‑set licensing models, product line‑ups, performance benchmarks, ecosystem maturity, and market prospects within the context of the country's digital‑economy and trust‑worthy computing initiatives.
This article explains how a CPU fetches and executes instructions, how processes and threads are created and managed, and why thread pools are crucial for efficiently handling short‑lived tasks on modern multi‑core systems.
During a computer freeze, the CPU isn’t simply idle; it may be trapped in a high‑priority interrupt handler or deadlocked kernel code, and the operating system’s scheduling and interrupt priorities determine whether the processor can be reclaimed, explaining why a simple infinite loop rarely causes a crash.
This article explains why computers freeze, describing how the CPU can become stuck in software loops, the crucial role of interrupts and their priorities, and how kernel‑level deadlocks can render a system unresponsive despite the CPU still running.
The article details a production incident where a containerized Java service experienced a CPU surge due to frequent young and full garbage collections, describing step‑by‑step diagnostics using Linux tools, jstack analysis, and code fixes that ultimately resolved the issue.
The team traced near‑100 % CPU spikes in an Elasticsearch cluster during stress tests to frequent JIT deoptimizations triggered by a switch‑based experiment routing logic, and resolved the issue by replacing the switch with a function map, which eliminated deoptimizations and stabilized CPU usage.
The article explains the various AI‑capable chips such as CPUs, GPUs, FPGAs, NPUs, and TPUs, compares their performance and efficiency, describes heterogeneous CPU+xPU solutions, and provides market share data while highlighting the growing adoption of specialized AI accelerators.
This article explains the key performance metrics of CPUs, GPUs, and graphics cards, shows how ladder charts are built from benchmark data, and provides practical tips for choosing the right hardware for desktops and laptops based on these rankings.
This guide explains how to analyze Linux load situations—whether CPU and load are both high or CPU is low while load remains high—by using commands like top, vmstat, iostat, sar, and jstack, and provides practical troubleshooting steps for common I/O‑related issues.
This article explains how CPU core count, frequency, cache, GPU shader count, memory bandwidth, and graphics card VRAM affect performance, and presents 2023 desktop and laptop performance ladder charts to help users compare and choose suitable hardware for their needs.
This article demonstrates how to use Alibaba's open‑source Java diagnostic tool Arthas to quickly locate and fix high CPU usage in a Java application, covering installation, attaching to a JVM, using dashboard, thread, jad, watch, and ognl commands, and interpreting the results.
This article reviews the evolution of mainstream CPU performance benchmarks such as SPEC and TPC, compares their methodologies and tools, discusses challenges in evaluating heterogeneous CPUs, and outlines future research directions, providing a comprehensive overview for researchers and practitioners.
This article explains why Linux performance issues arise, examines hardware, OS, network and application factors, outlines RAID choices, details OS and kernel tuning, describes the roles of ops staff, architects and developers, and provides a step‑by‑step troubleshooting workflow to improve system responsiveness and stability.
Android ANR occurs when the UI thread is blocked, triggered by time‑outs such as KeyDispatch, Broadcast, Service or ContentProvider, often caused by long I/O, deadlocks, Binder calls or resource exhaustion; diagnosing involves examining traces.txt, thread states, CPU/memory metrics, and using tools like Looper logs, Choreographer, or Tencent Matrix to prevent future freezes.
This article examines the fundamental differences between CISC (x86) and RISC CPU architectures, compares global market shares of Intel, AMD, and domestic Chinese processors, and evaluates the performance, ecosystem, and security advantages of leading CPUs such as HaiGuang in various computing scenarios.
The article uses a vivid CPU‑as‑a‑factory metaphor to explain how instruction pipelines work, why they improve performance, how pipeline depth affects speed and power, and what structural, data, and control hazards arise when multiple instructions share hardware resources.
This article examines a real‑world case where a serverless instance’s automatic scaling was instantly overwhelmed, causing high CPU usage, frequent Full GC and JVM crashes, and then demonstrates how Sentinel’s system‑level rules can mitigate the overload and improve cold‑start performance.
This guide explains how to select desktop computer parts—including CPU, GPU, motherboard, memory, storage, power supply, and cooling—by evaluating usage, performance tiers, specifications, brand options, and compatibility, while also noting which components can be safely bought second‑hand.
The article argues that PCI‑Express specifications, controllers, and switches must adopt a coordinated two‑year release cadence that matches CPU, GPU, and accelerator roadmaps, urging the PCI‑SIG to accelerate to PCI‑Express 7.0 to meet the bandwidth demands of modern data‑center and AI workloads.
This article explains how Linux performance depends on hardware, OS configuration, and application design, detailing CPU, memory, disk I/O, network bandwidth, RAID choices, kernel tuning, file‑system selection, and the roles of operators, architects, and developers in a systematic optimization workflow.
This article walks through how Didi identified excessive CPU consumption by ClickHouse background move threads, diagnosed the root cause using top and pstack, and applied a lightweight code guard that reduced CPU load from 30% to under 5%, improving overall cluster performance.
This article explains how to identify and resolve Linux performance bottlenecks by examining hardware resources, operating‑system settings, storage configurations, network bandwidth, and application behavior, and it outlines a systematic troubleshooting workflow for administrators, architects, and developers.
Modern CPUs use multi‑level cache memory to bridge the speed gap with main memory, relying on temporal and spatial locality, and employ the MESI protocol with states M, E, S, I to maintain coherence across cores, while techniques like store buffers and memory barriers mitigate latency and ordering issues.
By adding a guard that skips the costly part‑scan in MergeTreePartsMover::selectPartsForMove when disk usage is below the threshold and no MoveTTL is set, Didi reduced BgMoveProcPool thread CPU consumption from about 30 % to under 4 %, halving overall node CPU load and improving ClickHouse’s PB‑scale performance.
This guide walks you through essential Linux monitoring tools—htop/top for CPU usage, /proc files for hardware details, uptime and sar for load averages, pidstat for per‑process metrics, strace for system calls, lsof for open files, and network utilities like netstat and ss—providing commands, options, and interpretation tips to help you diagnose performance issues efficiently.
This article explains how Data Processing Units (DPUs) provide a low‑power, cost‑effective alternative to CPUs and GPUs for data‑centric workloads in modern data centers, detailing their architecture, programmability, and the performance and TCO benefits they bring.
The article reflects on how programming has become increasingly abstract, causing developers to overlook the CPU, memory, and low‑level architecture, and argues that revisiting these fundamentals is essential for deeper technical competence in today's software industry.
Chinese researchers used generative AI to design Qǐ Méng 1, the first completely self‑generated CPU chip that runs Linux and rivals early Intel 486 performance, showcasing the rapid rise of AI‑driven semiconductor design.
The article reflects on why modern programmers seldom think about the CPU, tracing the historical shift from assembly to high‑level languages, and argues that understanding low‑level architecture, registers, and memory remains essential despite the growing abstraction layers in software development.
Cache consistency spans icache‑dcache synchronization, multi‑CPU cache coherence, and device‑CPU interactions; the article explains the MESI protocol, demonstrates performance impacts with multithreaded code, explores prefetching, false sharing, mapping strategies, and practical tips for writing cache‑aware software.
This article explains how software performance events in the Linux kernel affect application performance, demonstrates how to list, count, and trace these events with perf, and shows how to visualize the results using FlameGraph to pinpoint bottlenecks such as cache misses, context switches, and page faults.
This article explains the multiple layers of CPU cache consistency, the MESI protocol, and how improper cache handling can dramatically slow programs, then demonstrates performance gains through code examples, prefetching, false‑sharing avoidance, and DMA strategies, offering practical guidance for low‑level optimization.
This article provides a comprehensive overview of the Xinchuang industry, detailing the fundamental concepts, architectures, and classifications of CPUs, GPUs, and storage devices, and explains how these core hardware components support the goal of achieving self‑controlled, secure information technology in China.
The article recounts a production incident where a Java service’s CPU surged to 1200%, detailing how top, jstack, and jmap were used to trace the issue to a missing parameter that caused a full‑table scan, prolonged GC pauses, and ultimately a system freeze.
The article explains how modern CPUs reorder instructions at compile‑time and runtime, the role of store buffers and invalid queues, why memory barriers are needed for visibility across cores, and compares sequential consistency guarantees on x86 versus ARM/Power architectures.
The 2023 desktop CPU ladder chart ranks Intel and AMD processors by multi‑core performance, helping users quickly compare generations and choose the most suitable CPU for gaming or productivity based on benchmark rankings and recommended motherboard pairings.
This article provides a comprehensive overview of ARM's processor architectures—including the A, R, and M profiles—detailing the evolution of major Cortex‑A series CPUs, the big.LITTLE concept, and the Mali GPU families, while also offering references to related technical reports and resources.
This guide explains how to pinpoint the MySQL statements that use the most CPU by mapping OS thread IDs to MySQL sessions, querying performance_schema and information_schema, and reviewing the execution plan to identify optimization opportunities.
The article explains how DPUs, as low‑power, high‑efficiency data‑processing units, complement CPUs and GPUs in modern data centers, reducing total cost of ownership while handling data movement, security, and analytics tasks more effectively than traditional processors.
A Java backend developer investigates sudden CPU spikes caused by hidden Nacos client threads, traces the issue through thread dumps and code analysis, explores Raft network partition behavior, and implements a fix that checks and recreates Nacos connections to prevent unnecessary thread creation.
A B‑station creator nicknamed “焊武帝” spent two and a half years hand‑crafting a fully functional CPU called “初芯”, detailing its low‑cost components, technical specifications, unique dual‑channel memory design, development hurdles, and its role as a proof‑of‑concept for future commercial processors.
This guide walks you through the prerequisites, step‑by‑step console and kubectl procedures, YAML configuration, and post‑deployment verification needed to run a CPU‑only Stable Diffusion model on Alibaba Cloud Container Service (ACK) and optionally switch to a GPU‑enabled version.
This article details the background, problems, and comprehensive refactoring plan for the xGis web‑based 3D map library, covering event classification, API design, layer interaction proxy, CPU/GPU picking implementations, performance trade‑offs, and future optimization directions.
The article provides a comprehensive overview of China’s domestic CPU ecosystem, explaining the role of CPUs as the digital foundation, comparing CISC and RISC instruction sets, and detailing the product lines and strategies of major manufacturers such as Huawei Kunpeng, HaiGuang, Feiteng, and Loongson, while concluding with market trends and competitive analysis.
This guide explains how to use Linux tools such as htop, top, uptime, sar, strace, free, pidstat, lsof, and Docker commands to monitor CPU, load average, memory, processes, network throughput, socket states, and database connections, helping you diagnose performance issues and map container PIDs to host PIDs.
This article explains common scenarios that cause MySQL (and related services) to consume 900% CPU, outlines step‑by‑step diagnosis using tools like top and show processlist, and provides practical remediation such as killing offending threads, adding missing indexes, disabling slow‑log, and leveraging Redis caching to bring CPU usage down to acceptable levels.
This guide explains how to use Linux tools such as htop, top, uptime, sar, pidstat, free, ps, lsof, netstat, and ss to monitor CPU details, load averages, memory usage, process information, PID mappings in containers, swap, inode statistics, network throughput, socket states, and database connection counts, providing practical commands and interpretation tips for effective system performance analysis.
This article explains common scenarios that cause CPU usage to soar above 200% in production, outlines step‑by‑step diagnosis and remediation for MySQL and Java processes, and shares real‑world case studies with command‑line tools, indexing, caching, and code adjustments to bring CPU load back to normal levels.
This guide presents a comprehensive collection of Linux commands and techniques for monitoring CPU, memory, network interfaces, I/O performance, processes, and system health, explaining each metric's meaning and offering practical examples to help administrators diagnose and optimize their servers efficiently.
The article explains how X86 (CISC) and ARM (RISC) CPU architectures differ in performance goals, power consumption, application domains, instruction set complexity, and market trends, highlighting their respective strengths in servers, PCs, mobile devices, and emerging data‑center workloads.
The article provides a detailed overview of NVIDIA's Grace CPU Superchip, describing its Arm‑based architecture, NVLink‑C2C interconnect, scalable coherency fabric, high‑bandwidth LPDDR5X memory, extensive I/O options, and software ecosystem, highlighting its suitability for HPC and AI workloads.
This article provides a comprehensive overview of China's leading domestic CPU vendors—including HaiGuang, Kunpeng, Loongson, Shenwei, Feiteng, and Zhaoxin—detailing their architectures, performance characteristics, market positioning, and the national initiatives that support their development.
The article details a sudden CPU spike in a Java backend service using Nacos, walks through diagnosing the offending thread with top and jstack, analyzes Nacos client thread creation and scheduled gray‑config tasks, explains Raft network partition handling, and presents a fix that checks config health and avoids unnecessary thread creation.
This article explains Linux load average, covering how it is calculated, its relationship with CPU usage, and how the kernel exposes load data to applications.
This article provides a comprehensive analysis of CPU technology, covering basic concepts, classification by instruction set and application, major architectures such as x86, ARM, RISC‑V, and POWER, and examines the upstream and downstream supply chain dynamics shaping the worldwide CPU industry.
This article explains the concept of CPU turbo boost, why single‑core performance metrics can be misleading, how different CPUs vary in base frequency and cache, and how turbo technology automatically raises clock speeds within safe limits to improve overall processing power.
This article provides a comprehensive overview of the Xinchuang industry’s hardware fundamentals, detailing CPU architecture and operation, instruction set classifications, GPU concepts and workflows, storage categories, and the distinction between independent and integrated GPUs, while also noting related promotional resources.
This guide explains Linux performance fundamentals—including throughput, latency, average load, CPU context switching, memory management, swap behavior, and the essential monitoring tools such as vmstat, pidstat, perf, and strace—while providing concrete command examples and troubleshooting steps.
This article breaks down nine essential techniques—ranging from faster CPU execution and effective caching to reducing interrupts, memory copies, and lock contention—to help developers systematically improve software performance across hardware and software layers.
The article provides a comprehensive technical overview of NVIDIA's Grace Hopper Superchip, detailing its heterogeneous CPU‑GPU design, high‑bandwidth NVLink‑C2C interconnect, performance advantages for HPC and AI workloads, programming model, and the architectural innovations that enable unprecedented scalability and productivity.
Intel’s new On Demand service lets customers unlock hidden accelerators and security features in Sapphire Rapids Xeon Scalable CPUs through either pay‑per‑use or one‑time license models, echoing a similar desktop upgrade program from 2010 that ultimately failed to gain traction.
The article analyzes post‑Moore challenges for server CPUs, discusses the shift from general‑purpose to specialized processors, highlights architectural innovations, chiplet integration, edge‑computing demands, and the evolving strategies of major vendors to improve performance, power efficiency, and scalability.
Linux cgroups, a kernel mechanism for grouping and controlling processes, enable fine-grained resource allocation, monitoring, and isolation, forming the foundation of container technologies like Docker and Kubernetes; this guide explains their concepts, hierarchies, subsystems, versions, configuration, and practical usage on CentOS.
Adding more RAM can improve performance only when memory is a bottleneck; if your system already has sufficient memory, extra RAM won’t make the CPU run faster, though it does allow more programs to run simultaneously, while insufficient memory can severely slow down tasks.
This article provides a comprehensive overview of China's six leading domestic server CPU manufacturers, detailing their instruction‑set classifications, product lineups, performance specifications, ecosystem integration, and market positioning, and predicts short‑term beneficiaries and long‑term industry trends.
A high‑CPU anomaly on a Spark‑enabled machine was traced through application checks, network TIME_WAIT analysis, and Airflow inspection, leading to kernel tweaks and an Airflow configuration change that finally restored normal CPU usage.
This comprehensive guide explains Linux performance optimization by defining key metrics such as throughput and latency, interpreting average load, analyzing CPU context switches, memory management, and I/O behavior, and recommending practical tools and techniques—including vmstat, pidstat, perf, and dstat—to identify and resolve bottlenecks.
The article provides a comprehensive analysis of the 2022 CPU industry chain, market size, global landscape, and major vendors, covering the dominance of x86, the rise of ARM, Intel and AMD market dynamics, UMA attempts, and emerging architectures such as RISC‑V and Apple’s M1.
This guide explains how to analyze and troubleshoot situations where Linux systems show high load averages despite low CPU usage, covering common load analysis methods, key commands like top, vmstat, iostat, sar, and ps, and practical solutions for I/O bottlenecks and D‑state processes.
Huawei’s Kunpeng processor adopts the ARM RISC architecture, contrasting with traditional CISC CPUs from Intel and AMD, and the article explains how RISC’s simplified, fixed-length instruction set improves performance, reduces hardware complexity, and aligns with modern computing demands.
FastDeploy is an open‑source toolkit that standardizes AI model APIs and enables developers to deploy vision, NLP, and speech models on diverse hardware—including GPUs, CPUs, Jetson, ARM, and various NPUs—using just three lines of code or a single command, while delivering end‑to‑end performance optimizations.
This article provides a comprehensive overview of how computers operate, covering CPU instruction cycles, memory organization, endianness, compiler translation, operating‑system interaction, cache levels, storage tiers, and the principles of temporal and spatial locality that drive modern performance optimizations.
The article explains how Huawei's Kunpeng processor, built on the Arm RISC architecture, overcomes the complexity and inefficiency of traditional CISC CPUs by using a simplified instruction set, fixed‑length commands, and better power‑performance balance, highlighting its technical advantages and industry relevance.
This guide explains how to monitor Linux system performance by using core commands such as top, vmstat, iostat, and sar to evaluate CPU usage, memory allocation, I/O activity, and network traffic, while also covering load interpretation, cache behavior, huge pages, zero‑copy techniques, and practical command examples.
The article provides a comprehensive overview of the role of CPUs and GPGPUs in modern server architectures and AI workloads, discussing hardware fundamentals, instruction set architectures, market trends, and the emerging importance of heterogeneous computing for high‑performance and energy‑efficient processing.
Learn how to use Linux’s top command to dynamically monitor process activity, interpret CPU, memory, and swap statistics, customize displayed columns, and apply useful shortcuts for sorting and filtering, enabling effective real-time system performance analysis and troubleshooting.
