When a midnight CPU alarm triggered, I logged into the server, identified runaway Java processes, profiled the JVM, refactored a costly sorting algorithm, added database indexes, containerized the service, and set up Prometheus alerts, ultimately reducing CPU usage below 30% and restoring millisecond response times.
This article walks readers through the five essential computer components—input devices, CPU, memory, storage, and output devices—explaining how they interact via the system bus to process a simple keystroke, illustrating data flow with diagrams, real‑world analogies, performance tips, troubleshooting tricks, and practical examples like taking a photo.
This article explains how to measure, analyze, and improve CPU usage in software by examining key metrics, choosing efficient algorithms and data structures, leveraging compiler options, exploiting cache behavior and SIMD vectorization, and applying practical case studies with Linux profiling tools.
This article provides an in‑depth overview of CPU performance metrics, practical optimization techniques—including algorithm selection, compiler flags, cache‑aware programming, and vectorization—along with real‑world case studies and a detailed survey of Linux profiling and analysis tools for developers.
This article explains the principles of CPU cache, the multi‑level memory hierarchy, virtual memory, data consistency, and concurrency control mechanisms, illustrating how they together bridge the speed gap between the fast processor and slower memory/storage in modern computer systems.
This article provides a comprehensive analysis of modern server architecture, covering the evolution from CISC to RISC, the rise of heterogeneous computing with GPUs and accelerators, diverse form factors, core component technologies, reliability mechanisms, performance benchmarking, certification standards, and emerging trends such as liquid cooling and AI‑native designs.
The article explains how 1960s batch systems suffered from CPU waste due to polling I/O devices, how IBM 704’s overflow flag inspired automatic error handling, and how the concept evolved into hardware interrupts with a concrete design, interrupt types, and vector table implementation.
The article explains how CPU pipelines, cache misses, branch‑prediction failures and lock contention cause non‑linear usage spikes, illustrates common pitfalls such as infinite loops, lock‑heavy spinning and catastrophic regex backtracking, and offers practical detection with perf and three rules—avoid busy‑waiting, use cache‑friendly layouts, and limit thread contention.
This article analyzes the Xinchuang hardware ecosystem and server industry from 2024 to 2026, covering supply‑chain structure, shipment growth, market share, competitive tiers, downstream application demands, and the technical and ecological challenges that hinder full domestic substitution.
When a midnight CPU alarm threatened a core Java service, I walked through rapid system checks, JVM profiling, algorithm refactoring, database indexing, Docker isolation, and enhanced monitoring to bring CPU usage back below 30% and restore service stability.
The article explains how early batch-processing systems relied on inefficient polling of slow I/O devices, describes the inspiration from IBM 704's overflow flag, and details the invention and implementation of hardware and software interrupts, including interrupt types, vector tables, and handler functions, to enable efficient CPU‑device interaction.
This article explains scientific notation, the IEEE‑754 floating‑point standard, the structure of FP32 and FP64 numbers, and how computational power is measured using FLOPS, illustrating CPU and GPU FP32 performance calculations and why FP32 is the common benchmark for AI workloads.
CPU cache, a multi‑level SRAM memory positioned between registers and main memory, evolved from non‑existent in early CPUs to sophisticated L1‑L4 hierarchies, addressing the massive speed disparity between processors and RAM by exploiting spatial and temporal locality to dramatically boost overall system performance.
The article explains how CPU computation latency arises from memory speed, bandwidth, and access delays, detailing the relationships among memory, bandwidth, and latency, and examines key factors such as clock frequency, pipelining, parallelism, cache hit rate, and signal propagation distances that together determine overall system performance.
This article introduces the basic structure of a general‑purpose CPU used in AI chips, describing the arithmetic‑logic unit (ALU), the different types of registers, and the controller, while also directing readers to extensive AI‑chip technical report collections for deeper study.
This article explains the background of tenant creation failures caused by insufficient CPU resources in OceanBase, details the calculation of usable CPU in version 4.x, shows how to query CPU usage with SQL, describes related configuration parameters, and provides step‑by‑step procedures for modifying cpu_count and testing over‑commit scenarios across different OceanBase versions.
This article provides a comprehensive analysis of China's Xinchang server industry, covering the upstream component supply chain, mid‑stream manufacturers, downstream users, shipment statistics, market share evolution, competitive tiers, application demands, and the technical and ecological challenges facing domestic CPU and GPU development.
When a Linux server's CPU spikes to 100%, this guide walks you through a systematic investigation—from identifying the high‑load process and pinpointing the offending Java thread to applying a streamlined shell script—so you can resolve the issue and restore normal performance.
The fourth part of a four‑article series provides a detailed analysis of six Chinese CPU manufacturers—Huawei Kunpeng, Phytium, HaiGuang, Zhaoxin, Loongson, and ShenWei—covering their processor architectures, product lineups, key performance metrics, recent releases, and future development plans up to 2026.
The article analyzes current server market dynamics, covering rising CPU core counts, accelerating network speeds, expanding SSD capacities, evolving DDR5 memory architectures, and the competitive landscape of AI‑focused GPUs as the industry prepares for 2025.
This guide walks you through Linux's directory layout, how to inspect CPU details via /proc, monitor utilization with top, retrieve version, memory and disk statistics, manage character sets, control services, and use common commands for file handling, permissions, networking, and process management.
This article walks through a real‑world incident where a PHP service consumed over 80% CPU, detailing how to identify the offending processes with htop, examine their status, trace system calls with strace, inspect file descriptors via lsof, and ultimately locate and correct a looping SQL query that caused the overload.
This guide walks through identifying Java processes that cause high CPU load, extracting the hottest threads with top and jstack, analyzing JVM memory regions, interpreting GC logs, and applying practical JVM tuning parameters and tools such as jmap, jstat, and MAT to resolve performance bottlenecks.
This article documents a step‑by‑step investigation of a compromised Linux server that exhibited 100% CPU usage, detailing process, network, and startup‑service analysis, the discovery of a cryptomining malware, and the complete removal procedure.
This guide explains how to analyze and troubleshoot situations where a Linux system shows high load averages despite low CPU usage, covering common load analysis methods, key commands like top, vmstat, iostat, and practical solutions for I/O bottlenecks and stuck processes.
This article walks through a real‑world Java CPU‑usage issue, showing how top, thread ID conversion, and jstack were used to pinpoint a faulty loop in LoguUtil, then verifies the fix restores normal CPU consumption while emphasizing the importance of performance testing.
The article explains how to troubleshoot extreme CPU usage in MySQL and Java processes, detailing step‑by‑step diagnostics with top, show processlist, jstack, and practical fixes such as adding missing indexes, disabling slow logs, using caches, and correcting busy‑loop code to bring CPU consumption back to normal levels.
The article examines the El Capitan supercomputer unveiled at SC24, detailing its AMD CPU‑GPU hybrid architecture, benchmark results, its dominance in the November 2024 Top500 list, and the broader implications for high‑performance computing, AI workloads, and the competitive landscape between AMD and NVIDIA.
This article provides a comprehensive overview of server fundamentals, covering the definition of a server, its classification by form factor, CPU architecture, and usage, as well as detailed explanations of hardware components like CPU, memory, storage, I/O, and networking devices.
This guide explains why MySQL and Java processes can suddenly consume 900% CPU, walks through systematic diagnosis using Linux tools, and provides concrete remediation steps such as indexing, caching, thread analysis, and code adjustments to bring CPU usage back to normal levels.
This article explains why mastering assembly language is crucial for understanding how computers execute code, covering the nature of low‑level languages, CPU instruction encoding, registers, memory models such as heap and stack, and walks through a complete x86 example with detailed instruction analysis.
This article compares the major instruction set architectures—x86, ARM, and RISC‑V—explaining their CISC versus RISC philosophies, historical evolution, technical trade‑offs, and the current market landscape of domestic and global CPU vendors.
At Computex 2024, AMD showcased its latest CPU, GPU, and AI‑accelerated technologies—including the high‑performance Zen 5 core, second‑generation XDNA NPU with 50 TOPS, the Ryzen 9000 consumer processor, the AI‑PC Strix Point platform, Versal AI Edge Gen 2, the upcoming MI‑series AI GPUs, and the new UA‑Link interconnect—highlighting the company’s roadmap for next‑generation computing and AI workloads.
This guide explains why MySQL or Java processes can consume 700‑900% CPU in production, walks through step‑by‑step diagnosis using Linux tools, and provides concrete remediation techniques such as indexing, caching, thread analysis, and code adjustments to restore normal performance.
The article analyzes the limits of the von Neumann model and Moore's law, explains how instruction set complexity defines processor categories, and argues that integrating CPUs, GPUs, FPGAs, DPUs and ASICs into a super‑heterogeneous ecosystem—driven by Intel, NVIDIA, ARM and emerging trends—will shape the future of computing through diverse workloads, AI demand, green efficiency and a global compute network by 2030.
This comprehensive guide introduces the core concepts of server hardware, covering CPU architectures, memory, storage devices and RAID configurations, as well as network interface cards, their classifications, functions, and common standards, providing a solid foundation for understanding modern data center infrastructure.
This article explains the background, creation, and detailed parameters of Java's ThreadPoolExecutor, walks through its task execution flow, warns against using Executors factory methods, and provides practical formulas for setting core pool sizes based on CPU‑bound or I/O‑bound workloads.
This guide walks through real‑world scenarios of high CPU and memory alerts, demonstrating how to use Linux's top tool, interpret its detailed output, convert thread IDs, and leverage jstack dumps to pinpoint and resolve performance bottlenecks.
This article walks you through a systematic approach to identify the root cause of a Linux server's CPU hitting 100%, from pinpointing the high‑load process with top, tracing the responsible business code, to using a custom shell script that streamlines thread analysis and resolves the overload.
This article provides a complete Bash script that gathers Linux system metrics—including IP address, CPU core count, utilization percentages, load averages, memory and swap usage, and disk I/O statistics—while explaining each command (ifconfig, grep, awk, top, vmstat, free, iostat, uptime) and how the script assembles the results.
This article introduces x86 assembly language, explaining its historical origins, the role of CPU registers such as EAX and ESP, the heap and downward‑growing stack memory models, and demonstrates basic stack‑frame operations like push, call, mov, add, pop, and ret through a simple compiled example.
This article explains the fundamentals of CPUs, covering their definition, core functions, internal structure, registers, instruction cycles, assembly language, branching, and how they interact with memory and I/O devices to execute programs.
This article breaks down the official and tested PC hardware requirements for Black Myth: Wu Kong, covering CPU, GPU, RAM, and ray‑tracing needs across 1080p, 2K, and 4K resolutions, and offers practical build recommendations for each performance tier.
This article presents a practical guide for backend developers to troubleshoot Linux performance problems, covering essential analysis tools, a systematic diagnosis method, and detailed checklists for CPU, memory, disk I/O, and network I/O issues.
This guide walks you through identifying a CPU‑mining malware infection on a Linux server, from spotting abnormal CPU usage with top, tracing the malicious executable, disabling its cron job, and safely cleaning the infected files and processes.
This article outlines practical troubleshooting steps for eight frequent production problems—including OOM, CPU spikes, interface timeouts, index failures, deadlocks, disk issues, MQ backlogs, and API errors—providing clear guidance and code snippets to help engineers quickly identify root causes and resolve them.
The article presents a concise mind‑map of essential Linux performance tools and a flexible troubleshooting workflow, guiding backend developers through CPU, memory, disk, and network issues by using utilities such as top, oprofile, slabtop, iotop, netstat, and strace to quickly pinpoint and resolve bottlenecks.
This article explains the evolution of CPU cache, its underlying principles of temporal and spatial locality, various cache architectures, implementation details, and practical considerations such as cache line size and replacement policies, providing a comprehensive overview for developers and computer engineers.
From raw binary on punched tape to mnemonic assembly and then to high‑level constructs like if, while, and functions, programmers created recursive grammars that compile source code into abstract syntax trees, which a compiler translates back into machine instructions, illustrating how recursion underpins both programming language design and computation.
The Venado supercomputer, unveiled at Los Alamos, combines Nvidia Grace CPUs, Hopper GPUs, HPE Slingshot interconnects, and massive memory bandwidth to achieve a 15.6‑petaflop FP64 peak, illustrating the evolving balance between CPU and GPU workloads in modern high‑performance computing.
This article explains the role of the CPU, its internal structure, key components like the control unit and ALU, registers, program counter, and how instructions are fetched, decoded, executed, and written back, using clear diagrams and examples.
This article outlines the main directions for server performance tuning—CPU, memory, disk, and network—explains the typical workflow of metric collection, bottleneck analysis, and parameter optimization, and provides a curated list of recent CPU industry reports and technical resources.
The 2024 China server CPU industry overview analyzes the dominance of X86 and ARM ecosystems, presents market size growth from 2018 to 2028, examines competitive advantages of domestic vendors, and discusses policy-driven demand and pricing challenges shaping the domestic CPU market.
This guide maps Linux kernel subsystems to key performance metrics and presents a curated set of CPU, memory, disk I/O, and network tools—complete with visual charts, metric explanations, and practical notes for effective system analysis.
At Computex 2024 AMD showcased its latest Zen 5 CPU core, second‑generation XDNA NPU with 50 TOPS AI performance, the consumer‑grade Ryzen 9000 series, AI‑focused Strix Point processors, Versal AI Edge Gen 2, upcoming AI GPUs like MI325X/MI350/MI400, and the new UA‑Link 1.0 networking standard.
This article explains common scenarios that cause MySQL or Java processes to consume 900% CPU, walks through step‑by‑step diagnosis using Linux tools, and provides concrete optimization techniques such as indexing, caching, thread analysis, and code adjustments to bring CPU usage back to normal levels.
The article investigates undocumented x86 opcodes, describing a depth‑first search that uses page‑faults to locate hidden instruction boundaries, and reports finding dozens of executable but undocumented instructions on Intel and AMD CPUs, highlighting potential security risks and the need for vigilant hardware analysis.
The article walks through real interview scenarios where MySQL or Java processes consume 900% CPU, detailing step‑by‑step diagnosis with top, processlist, jstack, and concrete remediation such as adding indexes, using caches, fixing busy loops, and tuning memory.
This guide walks you through Linux's built‑in utilities—such as cat, free, vmstat, lsblk, ip, ethtool, top, htop, and Glances—to display and analyze CPU, memory, storage, and network information, helping you monitor system health and plan upgrades.
This article investigates two real‑world performance incidents—one caused by excessive disk I/O from a misconfigured Filebeat and another by kernel memory‑fragmentation bugs triggered by a trace feature—detailing observations, Linux diagnostic commands, analysis, and practical remediation steps.
By following Ben Eater’s step‑by‑step tutorial, a non‑computer‑science student assembled a fully functional 8‑bit CPU on a breadboard using a 555‑timer clock and TTL chips such as 74LS173 and 74LS245, spending two months on half‑hour daily sessions to achieve a working processor that deepened their grasp of computer architecture and basic electronics.
CPU efficiency depends on low CPI and high cache‑hit rates, which can be measured on Linux using the high‑level perf utility or the low‑level perf_event_open syscall to read hardware performance counters for cycles, instructions, and cache‑miss statistics, revealing how often the processor falls back to slower memory.
This article explains how CPUs interpret binary signals as voltage levels, describes basic logic gates such as AND, OR, NOT, shows how they combine to perform arithmetic like addition, and clarifies that hardware itself lacks understanding, relying on human-designed instruction sets and compilers to give meaning to 0s and 1s.
This article introduces Linux perf, explains how to install it, demonstrates basic commands such as perf‑list, perf‑stat, perf‑top, perf‑record and perf‑report, and shows how to combine perf with flame‑graphs to locate CPU‑bound hotspots and other performance bottlenecks in applications and the kernel.
This article explains why threads are essential for performance, how to create and configure Java thread pools using the Executors utility, distinguishes CPU, IO, and scheduled pool types, and demonstrates monitoring techniques for latency and deadlock detection with practical code examples.
The article explains that a CPU merely reacts to voltage signals without any comprehension, illustrating how binary 0/1, logic gates, and combinational circuits form the basis of computation, and why compilers—not the CPU—interpret programming languages before execution.
This article explains server CPU memory controller architecture, detailing the six DDR4 channels, the differences between UDIMM, RDIMM, LRDIMM, and SO‑DIMM modules, how bandwidth is calculated, and the role of ECC memory in ensuring data integrity for enterprise systems.
This article details the migration of the Cloud Music desktop client from a legacy NEJ‑CEF hybrid to a React‑based architecture, outlines four major performance challenges, and explains the step‑by‑step optimizations—including API preloading, render memoization, virtual‑list replacement, and resource‑usage reductions—that cut startup latency by 48%, eliminated interaction stutter, and dramatically lowered CPU, GPU, and memory consumption.
GaussDB provides a fine‑grained resource control solution that lets administrators define CPU, memory, I/O, connection, concurrency, and storage limits at user, session, and statement levels, using resource pools, control groups, and GUC parameters to ensure multi‑tenant isolation, SLA compliance, and optimal cluster utilization.
Linux’s “watchdog: BUG: soft lockup – CPU#1 stuck” warning indicates a CPU soft lockup, caused by driver bugs, hardware faults, or kernel issues, and can be resolved by updating software, monitoring hardware, analyzing logs, and implementing preventive performance and hardware checks.
Since 2023 users have reported that Intel's flagship desktop CPUs i9-13900K and i9-14900K suffer stability problems, especially during gaming, which Intel attributes to non‑standard BIOS configurations on 600/700 series motherboards that disable critical thermal and power protections.
This article explains the basic functions of CPUs and GPUs, their advanced capabilities and real‑world applications, and compares their architectures, processing models, and roles in environments such as IoT, mobile devices, Kubernetes, and AI workloads.
This article compiles seven hands‑on Linux performance‑optimization practices—including hardware, kernel, and network tuning, diagnostic commands, memory accounting, swap usage, and TCP parameter adjustments—to help engineers quickly identify and resolve stability and speed issues in production environments.
This guide walks you through checking CPU usage, system load, resource consumption, problematic processes, system logs, and performance bottlenecks on a Linux server using common command‑line tools such as top, uptime, pidstat, strace, tail, and perf.
The talk outlines how modern data centers host diverse CPUs (Intel, AMD, Ampere, ARM), the multi‑layer performance‑tuning challenges this creates, and how Baidu Cloud’s one‑click Btune suite automates metric collection, bottleneck identification, and optimization across hardware, kernel, runtime, and application layers.
This article explains the architecture of server‑grade CPU memory controllers, covering memory channel counts, bandwidth calculations, the differences between UDIMM, RDIMM and LRDIMM modules, and the role of ECC in ensuring data integrity.
This guide introduces the Linux lscpu command, explains its syntax and common options, provides example outputs in default, parsable and extended formats, clarifies each field's meaning, and offers practical usage notes for accurate CPU information retrieval.
This article explains the fundamentals of a CPU, covering its definition, core functions, internal structure, registers, instruction cycle, assembly language basics, program counter, branching, flag registers, function calls, and how memory addressing enables array-like operations.
The article describes how the author followed Ben Eater’s step‑by‑step tutorial to hand‑assemble a functional 8‑bit CPU on a breadboard, detailing required components, sourcing parts in China, wiring procedures, and practical tips for beginners interested in computer architecture and electronics DIY.
This article explains common causes of extreme CPU usage in MySQL and Java applications, provides step‑by‑step troubleshooting methods using Linux tools and SQL commands, and presents real‑world case studies with concrete optimizations such as indexing, caching, and thread‑handling adjustments.
This guide walks through diagnosing excessive CPU load and memory consumption in Java applications, using tools like top, jstack, jmap, and jstat, and provides step‑by‑step solutions and JVM tuning parameters to reduce GC pauses and prevent full garbage collections.
This guide walks you through checking CPU utilization, system load, process resource consumption, tracing problematic processes, reviewing logs, and using performance tools to pinpoint and resolve high CPU usage on a Linux server.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, featuring larger dies, higher cost, no graphics, many more cores, ECC memory with many DIMM slots, multi‑CPU linking, and lower, more stable clock speeds.
Typical reasons for Java backend services hitting 100 % CPU include fetching massive data sets, misusing Kafka auto‑acknowledge, infinite loops or recursion, thread‑pool overload causing context‑switch thrashing, bulk file synchronization, lock‑order deadlocks, poorly designed regular expressions, and intensive real‑time calculations under high concurrency.
This article examines common reasons behind persistent 100% CPU usage in Java backend systems—ranging from excessive full GC and Kafka auto‑acknowledgment to dead loops, thread‑pool overload, massive file sync, deadlocks, inefficient regex and heavy real‑time calculations—offering practical diagnostics and solutions.
This article explains the meaning of 32‑bit and 64‑bit labels for CPUs, operating systems, software and integer types, shows how source code becomes machine code and a running process, and clarifies the memory‑addressing limits and compatibility rules of each architecture.
CPU, the brain of a computer, is a tiny chip that fetches, decodes, and executes instructions, comprising control units, ALU, registers, and interacts with memory, while supporting programming concepts like assembly, conditionals, loops, and function calls, all illustrated with diagrams and examples.
This article analyzes typical reasons why Java backend services experience sustained 100% CPU usage—such as bulk data retrieval, Kafka auto‑acknowledgement, infinite loops, excessive multithreading, massive file synchronization, deadlocks, inefficient regular expressions, and heavy real‑time calculations—and offers practical mitigation strategies.
This article explains the key Linux performance indicators—CPU, memory, disk I/O, file system, and network—describes how to monitor them with commands like top, vmstat, iostat, iotop, and smem, and provides practical guidance on interpreting the results to identify and resolve system bottlenecks.
This article examines eight common reasons why Java backend services experience 100% CPU usage—such as fetching excessive data, automatic Kafka acknowledgments, infinite loops, multithreaded imports, massive file syncs, deadlocks, inefficient regular expressions, and heavy real‑time calculations—and provides practical mitigation strategies.
This guide walks through systematic troubleshooting of Java applications by checking CPU, disk, memory, and network layers, using tools like jstack, jmap, vmstat, iostat, and tcpdump to pinpoint and resolve performance and stability problems.
Server CPUs differ from desktop CPUs in size, price, integrated graphics, core count, memory support, scalability, and clock frequency, with server chips being larger, more expensive, lacking integrated graphics, offering more cores, ECC memory, multi‑CPU interconnects, and lower base frequencies for stability.
After migrating workloads to a new CPU platform, unexpected performance regressions can occur, but Baidu Cloud's Btune tool provides automated, multi‑dimensional analysis and actionable optimization suggestions that helped a test program improve its execution time by 36.8% through memory and NUMA tuning.
This article explains what a CPU is, how it processes instructions through fetch‑decode‑execute stages, its internal components such as the control unit, ALU and various registers, the role of memory and program counters, and introduces assembly language concepts and branching mechanisms.
The article examines how CPUs, GPUs, and memory have long formed the core of PC hardware, discusses the emerging role of NPUs for AI processing, and describes Intel's Lunar Lake strategy of integrating memory with the processor to deliver faster, lower‑latency performance in upcoming AI‑focused PCs.
Tech blogger Inkbox demonstrates how to construct a fully functional 16‑bit CPU, complete with 128 KB RAM, a 128×128 pixel display, and a custom 23‑instruction assembly language called Excel‑ASM16, all implemented purely within Microsoft Excel without any VBA scripts or plugins.
The article analyzes the global CPU and GPU markets, showing Intel and AMD's overwhelming share, the rise of new data‑center players, key performance metrics for CPUs, the constraints of instruction‑set ecosystems, and emerging AI‑chip design trends that could open space for domestic Chinese manufacturers.
The article examines Nvidia's GH200 superchip and AMD's Instinct MI300, compares CPU, GPU, FPGA, and ASIC architectures, analyzes market share trends, and discusses opportunities for domestic chip makers in the rapidly evolving AI compute landscape.
This article demystifies the CPU by defining its role as the computer's brain, describing the fetch‑decode‑execute cycle, detailing its internal components such as the control unit, ALU and various registers, and explaining how instruction sets, assembly language, program counters, flags, function calls, and array addressing work together to run programs.
This article provides a comprehensive, step‑by‑step overview of CPU fundamentals, covering its definition, core functions, internal architecture, key registers, instruction execution stages, program counter behavior, conditional branching, flag registers, function calls, memory addressing, and the classic fetch‑decode‑execute pipeline.
