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569 articles · Page 5 of 6
Top Architect
Top Architect
Dec 29, 2020 · Operations

Comprehensive Guide to Java Runtime Error Checking: CPU, Disk, Memory, GC, and Network Troubleshooting

This article provides a step‑by‑step guide for diagnosing Java production issues by systematically checking CPU usage, disk health, memory consumption, garbage‑collection behavior, and network problems using common Linux tools and JVM utilities such as ps, top, jstack, jstat, vmstat, iostat, free, jmap, and tcpdump.

CPUGarbage CollectionMemory
0 likes · 21 min read
Comprehensive Guide to Java Runtime Error Checking: CPU, Disk, Memory, GC, and Network Troubleshooting
Liangxu Linux
Liangxu Linux
Dec 24, 2020 · Fundamentals

Why CPU Cache Matters: From Memory Access to False Sharing and Linux Scheduling

This article explains CPU architecture, cache hierarchy, the concept of cache lines, how false sharing degrades performance, mitigation techniques like cache‑line alignment, and the Linux scheduler's task prioritisation, virtual runtime, and run‑queue mechanisms for fair and real‑time execution.

CFSCPULinux scheduling
0 likes · 19 min read
Why CPU Cache Matters: From Memory Access to False Sharing and Linux Scheduling
Architects' Tech Alliance
Architects' Tech Alliance
Dec 18, 2020 · Fundamentals

Overview of China's Domestic CPU Landscape: History, Key Players, and Technical Highlights

This article provides a comprehensive overview of the development, major manufacturers, architectures, performance specifications, ecosystem building, and security features of China's domestic CPUs, tracing their historical evolution from the 1950s to the present and assessing their role in national technology independence.

CPUChinaHardware
0 likes · 18 min read
Overview of China's Domestic CPU Landscape: History, Key Players, and Technical Highlights
Liangxu Linux
Liangxu Linux
Dec 16, 2020 · Fundamentals

How Early CPUs Managed Memory: From 8086 Segmentation to Modern Paging

The article narrates a whimsical tour through CPU history, explaining how the 8086 used shared address/data pins and segmentation, how 32‑bit processors introduced separate buses and operating‑system multitasking, and how virtual memory, paging, and swapping evolved to support modern multi‑core systems.

CPUSegmentationoperating-system
0 likes · 9 min read
How Early CPUs Managed Memory: From 8086 Segmentation to Modern Paging
Architects' Tech Alliance
Architects' Tech Alliance
Dec 14, 2020 · Fundamentals

Server CPU Architecture, Platform Evolution, and Market Trends

The article explains the data flow and component interactions on server motherboards, details CPU and chipset roles, describes Intel's successive CPU platforms and manufacturing processes, and analyzes how these technological upgrades influence server configurations, market demand, and datacenter growth.

CPUDataCenterIntel
0 likes · 9 min read
Server CPU Architecture, Platform Evolution, and Market Trends
Liangxu Linux
Liangxu Linux
Nov 16, 2020 · Fundamentals

Unlocking the Secrets of x86/x64 CPU Registers: A Deep Dive

This comprehensive guide explores the myriad x86/x64 CPU registers—including general, flag, instruction, segment, control, debug, descriptor, task, and model‑specific registers—explaining their roles, how they interact in memory addressing, multitasking, system calls, and debugging, while highlighting key differences between 32‑bit and 64‑bit modes.

CPUcomputer architectureregisters
0 likes · 21 min read
Unlocking the Secrets of x86/x64 CPU Registers: A Deep Dive
Liangxu Linux
Liangxu Linux
Oct 22, 2020 · Fundamentals

Why CPU Access to Hard Drives Is So Slow: A Deep Dive into HDD, SSD, and I/O

Hard drives (HDD) and solid‑state drives (SSD) differ dramatically in latency; the article explains the orders‑of‑magnitude gap between CPU cache, memory, and disk access, details the I/O mechanisms (programmed I/O, interrupt‑driven I/O, DMA), and shows why mechanical drives are inherently slow.

CPUI/OSSD
0 likes · 11 min read
Why CPU Access to Hard Drives Is So Slow: A Deep Dive into HDD, SSD, and I/O
Liangxu Linux
Liangxu Linux
Oct 14, 2020 · Fundamentals

What Are the Minimal Building Blocks of a CPU? From Relays to Logic Gates

This article explains the fundamental hardware components of a CPU, starting with early relay‑based machines, describing basic logic gates, constructing simple adders and an ALU, detailing memory and registers, and illustrating the fetch‑decode‑execute cycle and the evolution of machine code to assembly language.

ALUCPUHardware Fundamentals
0 likes · 12 min read
What Are the Minimal Building Blocks of a CPU? From Relays to Logic Gates
dbaplus Community
dbaplus Community
Oct 11, 2020 · Operations

Mastering CPU and Load: A Practical Guide to Linux Performance Troubleshooting

This article explains how to monitor and interpret CPU usage and load average on Linux servers, details the calculations behind these metrics, illustrates their meaning with examples and images, and provides step‑by‑step troubleshooting methods for high load, high CPU, and high load with low CPU scenarios.

CPULinux monitoringLoad Average
0 likes · 19 min read
Mastering CPU and Load: A Practical Guide to Linux Performance Troubleshooting
Top Architect
Top Architect
Sep 27, 2020 · Operations

Comprehensive Guide to Java Runtime Error Checking and Troubleshooting (CPU, Memory, Disk, Network, GC)

This article provides a systematic, step‑by‑step guide for diagnosing and resolving Java runtime problems—including CPU spikes, memory leaks, disk I/O bottlenecks, network timeouts, and GC inefficiencies—by using native Linux tools and JVM utilities such as top, ps, jstack, jmap, jstat, iostat, vmstat, pidstat, netstat, ss, and tcpdump.

CPUGCMemory
0 likes · 22 min read
Comprehensive Guide to Java Runtime Error Checking and Troubleshooting (CPU, Memory, Disk, Network, GC)
Alibaba Cloud Developer
Alibaba Cloud Developer
Sep 15, 2020 · Big Data

Designing Nexmark: A Standard Benchmark for Stream Processing Performance

This article examines the challenges of existing stream‑processing benchmarks, introduces the open‑source Nexmark framework designed for reproducible, comprehensive performance testing, describes its metrics, query set, workload configurability, and presents experimental results on Flink, highlighting its role in advancing big‑data stream benchmarking.

CPUFlinkNexmark
0 likes · 14 min read
Designing Nexmark: A Standard Benchmark for Stream Processing Performance
Java Captain
Java Captain
Sep 1, 2020 · Operations

Comprehensive Guide to Java Online Fault Diagnosis: CPU, Disk, Memory, GC, and Network Issues

This article provides a detailed, step‑by‑step methodology for diagnosing and resolving common Java production problems—including CPU spikes, disk bottlenecks, memory leaks, garbage‑collection anomalies, and network timeouts—by leveraging native Linux tools and JVM utilities such as ps, top, jstack, jmap, jstat, iostat, vmstat, pidstat, and netstat.

CPUGCMemory
0 likes · 19 min read
Comprehensive Guide to Java Online Fault Diagnosis: CPU, Disk, Memory, GC, and Network Issues
Architects' Tech Alliance
Architects' Tech Alliance
Aug 16, 2020 · Fundamentals

Overview of Recent IT Hot Topics: Docker Service Terms, ARM Acquisition, and the Chinese Domestic CPU Landscape

The article reviews three major IT events—Docker's new service terms restricting entities on the US Commerce Department list, Nvidia's potential ARM acquisition and its impact on AI and supercomputing, and Intel's latest CPU and GPU technologies—while also explaining CPU fundamentals, CISC vs. RISC architectures, and the current state of China's domestic processor industry.

ARMCPUDomestic CPUs
0 likes · 12 min read
Overview of Recent IT Hot Topics: Docker Service Terms, ARM Acquisition, and the Chinese Domestic CPU Landscape
macrozheng
macrozheng
Aug 8, 2020 · Fundamentals

How CPUs Handle Interrupts: From 8259A PIC to APIC and Affinity

This article explains the CPU's interrupt mechanism, describing how hardware devices trigger interrupts, the role of the 8259A programmable interrupt controller, the evolution to APIC with I/O and Local APICs, and how interrupt affinity can be configured to improve multi‑core performance.

APICCPUPIC
0 likes · 9 min read
How CPUs Handle Interrupts: From 8259A PIC to APIC and Affinity
Architects' Tech Alliance
Architects' Tech Alliance
Aug 2, 2020 · Fundamentals

Evolution and Current Landscape of Chinese Domestic Operating Systems

This article traces the early emergence of Chinese Linux‑based operating systems, analyzes the reasons for their limited market impact, outlines the recent ecosystem improvements and policy support, and reviews key players, CPU developments, and the unified strategy behind modern domestic OS solutions such as UOS and Kylin.

CPUChinese TechnologyEnterprise Software
0 likes · 28 min read
Evolution and Current Landscape of Chinese Domestic Operating Systems
dbaplus Community
dbaplus Community
Jul 29, 2020 · Operations

Why CPU Idle ≠ Exhausted: Uncovering IO Bottlenecks in Java Services

A real‑world incident showed that a 0% CPU idle rate can mask severe disk IO wait, leading to thread exhaustion in a SpringBoot order service, and the article explains how IO, DMA, Java thread states, and various Linux network IO models interact while offering practical mitigation tactics.

CPUIOLinux
0 likes · 14 min read
Why CPU Idle ≠ Exhausted: Uncovering IO Bottlenecks in Java Services
Full-Stack Internet Architecture
Full-Stack Internet Architecture
Jun 15, 2020 · Fundamentals

Process and Thread Scheduling: Algorithms, Strategies, and Goals

This article provides a comprehensive overview of process and thread scheduling in operating systems, explaining the role of the scheduler, different scheduling algorithms such as FCFS, SJF, round‑robin, priority, multilevel‑queue and lottery, their classification for batch, interactive and real‑time environments, and the key performance goals like fairness, throughput and response time.

CPUProcess SchedulingScheduling Algorithms
0 likes · 31 min read
Process and Thread Scheduling: Algorithms, Strategies, and Goals
Efficient Ops
Efficient Ops
Jun 3, 2020 · Operations

Understanding Kubernetes vs VM Monitoring: CPU, Memory, Disk & Network

This article compares monitoring metrics for CPU, memory, disk, and network between traditional KVM-based servers and Kubernetes pods, explaining why their indicators differ, how resource isolation works, and what key metrics users should watch to diagnose performance bottlenecks.

CPUKubernetesMemory
0 likes · 11 min read
Understanding Kubernetes vs VM Monitoring: CPU, Memory, Disk & Network
Open Source Linux
Open Source Linux
May 24, 2020 · Operations

Understanding Server Hardware: Power, CPU, Memory, Disk, RAID & More

This article explains the essential components of a server—including power supply, CPU, RAM, storage, RAID cards, remote management modules, and motherboard—detailing their functions, typical configurations, and best‑practice considerations for reliable enterprise operations.

CPUMemoryRAID
0 likes · 9 min read
Understanding Server Hardware: Power, CPU, Memory, Disk, RAID & More
ITPUB
ITPUB
May 18, 2020 · Operations

Master Linux System Monitoring: Top, Perf, Sar, Vmstat, and More

This guide explains how to use a variety of Linux performance tools—including top, perf, sar/ksar, mpstat, uptime, vmstat, pidstat, time, cpustat, htop, atop, glances, nmon, pcp‑gui, collectl and colplot—to monitor CPU, memory, disk, network and process activity with concrete command examples and visualisations.

CPULinuxdiagnostics
0 likes · 21 min read
Master Linux System Monitoring: Top, Perf, Sar, Vmstat, and More
Efficient Ops
Efficient Ops
May 12, 2020 · Operations

Master Java Server Troubleshooting: CPU, Memory, Disk, GC & Network Issues

This guide walks you through systematic troubleshooting of Java server incidents covering CPU, memory, disk, garbage collection, and network problems, offering step‑by‑step command‑line techniques, analysis of thread stacks, GC logs, native memory tracking, and TCP diagnostics to pinpoint root causes efficiently.

CPUGCMemory
0 likes · 19 min read
Master Java Server Troubleshooting: CPU, Memory, Disk, GC & Network Issues
Architects' Tech Alliance
Architects' Tech Alliance
May 10, 2020 · Fundamentals

Server CPU, GPU, and Memory Basics

This article introduces the essential components of a server—CPU, GPU, and memory—explaining their roles, characteristics, and common configurations, especially for video processing and artificial intelligence workloads, while providing visual diagrams and further reading suggestions.

CPUGPUHardware
0 likes · 4 min read
Server CPU, GPU, and Memory Basics
Programmer DD
Programmer DD
Apr 30, 2020 · Fundamentals

Unlocking CPU Secrets: How Processors Execute, Cache, and Multithread

This article explains the core components and operation of a CPU, covering the fetch‑decode‑execute cycle, instruction sets, registers, pipeline and superscalar designs, multi‑core and hyper‑threading concepts, and the hierarchy of caches from registers to L3, providing a comprehensive fundamentals overview.

CPUPipeliningcache
0 likes · 14 min read
Unlocking CPU Secrets: How Processors Execute, Cache, and Multithread
Meituan Technology Team
Meituan Technology Team
Apr 16, 2020 · Databases

Analyzing and Optimizing MySQL Performance on Intel Skylake CPUs

Meituan’s DBA team discovered that Intel Skylake CPUs dramatically increased PAUSE‑instruction latency, causing MySQL’s ut_delay spin‑wait loops to consume most CPU cycles and reduce write throughput, and they restored performance by back‑porting MySQL 8.0’s spin_wait_pause_multiplier patch to 5.7, upgrading to CentOS 7, and moving to Cascadelake hardware.

CPUDatabaseLinux
0 likes · 18 min read
Analyzing and Optimizing MySQL Performance on Intel Skylake CPUs
Liangxu Linux
Liangxu Linux
Apr 1, 2020 · Operations

Understanding CPU Cores, Usage, and Load: A Practical Linux Performance Guide

This article explains CPU fundamentals, distinguishes physical and logical cores, shows how to retrieve CPU details on Linux, defines CPU usage and load average, offers practical thresholds, and provides step‑by‑step troubleshooting techniques for high user‑mode CPU consumption.

CPULoad Averageperformance monitoring
0 likes · 13 min read
Understanding CPU Cores, Usage, and Load: A Practical Linux Performance Guide
Open Source Linux
Open Source Linux
Mar 19, 2020 · Operations

Why Is My Server CPU at 99%? Pinpoint Java Thread Bottlenecks Fast

After an alert showed a data platform server’s CPU usage soaring to 98.94%, this article walks through a systematic investigation—from spotting the high‑load process with top, tracing the offending Java thread using pwdx and jstack, to optimizing the time‑conversion utility that caused the overload.

CPUDebuggingOperations
0 likes · 7 min read
Why Is My Server CPU at 99%? Pinpoint Java Thread Bottlenecks Fast
Java Backend Technology
Java Backend Technology
Mar 19, 2020 · Backend Development

Speed Up Java Debugging: One‑Click Tools to Pinpoint 100% CPU and Deadlocks

Backend developers often face sudden high CPU usage or thread deadlocks in production Java services, and this article introduces a set of one‑click scripts and practical examples that automate diagnosis, locate offending code lines instantly, and provide additional utilities for classpath conflicts, JVM monitoring, and runtime tracing.

CPUDeadlockDebugging
0 likes · 13 min read
Speed Up Java Debugging: One‑Click Tools to Pinpoint 100% CPU and Deadlocks
macrozheng
macrozheng
Feb 4, 2020 · Fundamentals

Unlocking Computer Fundamentals: From CPU Basics to Assembly Language Explained

Explore the essential building blocks of modern computing, covering CPU architecture, memory hierarchy, binary operations, compression techniques, operating system fundamentals, and assembly language, with clear explanations, diagrams, and code examples that demystify how hardware and software interact at the lowest level.

AssemblyCPUMemory
0 likes · 74 min read
Unlocking Computer Fundamentals: From CPU Basics to Assembly Language Explained
Efficient Ops
Efficient Ops
Jan 22, 2020 · Fundamentals

Why a Single Regex Can Crash Your Java Service: Understanding NFA Backtracking

An unexpected CPU spike in a Java service was traced to a complex URL‑validation regex whose NFA backtracking caused catastrophic performance, and the article explains the regex engine’s behavior, identifies the problematic pattern, and shows how to refactor the expression to eliminate excessive backtracking.

CPUNFARegex
0 likes · 12 min read
Why a Single Regex Can Crash Your Java Service: Understanding NFA Backtracking
Architects' Tech Alliance
Architects' Tech Alliance
Jan 17, 2020 · Fundamentals

Overview of Server Benchmark Standards: TPC and SPEC

The article explains the origins, metrics, and test suites of TPC and SPEC benchmarks, describes their various models for CPU, web, HPC and storage performance, shows how to query official results, and notes a promotional bundle of technical e‑books.

CPUOperationsPerformance Testing
0 likes · 9 min read
Overview of Server Benchmark Standards: TPC and SPEC
Didi Tech
Didi Tech
Jan 5, 2020 · Backend Development

Investigation and Optimization of High‑Frequency Go Service Timeout in Containers

The study traced severe Redis latency spikes in an 8‑core container to the Go runtime mistakenly reading the host’s CPU count, which created hundreds of threads and scheduler contention; limiting GOMAXPROCS to the container’s quota eliminated the jitter, while further gains were suggested by reducing HMGET calls, tuning GC, and upgrading Go.

CPUGOMAXPROCSGo
0 likes · 14 min read
Investigation and Optimization of High‑Frequency Go Service Timeout in Containers
Architects' Tech Alliance
Architects' Tech Alliance
Jan 1, 2020 · Fundamentals

Understanding CPU Execution, Architecture, and Multicore/Multithreading

This article explains how a CPU executes programs through the fetch‑decode‑execute cycle, describes instruction sets, registers, pipelines, superscalar and multithreaded designs, and details the cache hierarchy from registers to L3, providing a comprehensive overview of modern processor fundamentals.

CPUInstruction Setarchitecture
0 likes · 11 min read
Understanding CPU Execution, Architecture, and Multicore/Multithreading
Architects' Tech Alliance
Architects' Tech Alliance
Dec 28, 2019 · Artificial Intelligence

Understanding CPU vs GPU, GPU Parameters, and NVIDIA Architectures for AI and High‑Performance Computing

The article explains how CPUs and GPUs differ in architecture and workload handling, details key GPU specifications such as CUDA cores, memory bandwidth and floating‑point precision, reviews NVIDIA's product families and architectural evolution, and highlights the role of GPUs in deep learning training and inference while also mentioning a related technical ebook promotion.

AICPUCUDA
0 likes · 13 min read
Understanding CPU vs GPU, GPU Parameters, and NVIDIA Architectures for AI and High‑Performance Computing
Programmer DD
Programmer DD
Dec 26, 2019 · Fundamentals

Understanding CPU Architecture: From Instruction Cycle to Multicore Caches

This article explains how a CPU executes programs through the fetch‑decode‑execute cycle, describes instruction sets, registers, pipelines, superscalar and multithreaded designs, and details the hierarchy of caches from registers up to L3, providing a comprehensive overview of modern processor fundamentals.

CPUcachescomputer architecture
0 likes · 12 min read
Understanding CPU Architecture: From Instruction Cycle to Multicore Caches
Liangxu Linux
Liangxu Linux
Dec 22, 2019 · Fundamentals

How Simple Logic Gates Build a CPU: From Diodes to 4‑Bit Adders

This article explains how basic semiconductor concepts and diode‑based logic gates can be combined into simple arithmetic circuits, registers, and a minimal instruction set to construct a functional 4‑bit CPU, illustrating each step with diagrams and historical context.

CPUadderscomputer architecture
0 likes · 13 min read
How Simple Logic Gates Build a CPU: From Diodes to 4‑Bit Adders
IT Architects Alliance
IT Architects Alliance
Nov 25, 2019 · Fundamentals

Why a Complex URL Regex Can Max Out Java CPU and How to Fix It

A Java service suffered near‑100% CPU usage because a URL‑validation regular expression caused catastrophic backtracking, and the article explains the NFA engine behavior, identifies the regex flaws, and shows how to rewrite the pattern with possessive quantifiers to dramatically improve performance.

CPUNFARegex
0 likes · 12 min read
Why a Complex URL Regex Can Max Out Java CPU and How to Fix It
Architects' Tech Alliance
Architects' Tech Alliance
Nov 24, 2019 · Fundamentals

Overview of RISC, ARM, x86, Atom, MIPS, and PowerPC Processors

The article provides a comprehensive overview of RISC principles and compares major processor families—including ARM, x86, Atom, MIPS, and PowerPC—detailing their architectures, performance characteristics, market adoption, and licensing models while also mentioning related DSP technologies and reference resources.

ARMCPUMIPS
0 likes · 12 min read
Overview of RISC, ARM, x86, Atom, MIPS, and PowerPC Processors
Liangxu Linux
Liangxu Linux
Nov 4, 2019 · Fundamentals

How CPUs Execute Programs: From Fetch‑Decode‑Execute to Multicore & Cache

This article explains the core principles of CPU operation, covering the fetch‑decode‑execute cycle, instruction sets, registers, pipeline and superscalar designs, multithreading and multicore behavior, as well as cache hierarchy from registers through L1‑L3, illustrating how these mechanisms affect program execution.

CPUInstruction Setarchitecture
0 likes · 14 min read
How CPUs Execute Programs: From Fetch‑Decode‑Execute to Multicore & Cache
dbaplus Community
dbaplus Community
Sep 23, 2019 · Databases

Why Short Connections, Frequent INFO Calls, and Pipelines Hurt Redis Performance (and How to Fix It)

This article examines three common Redis performance pitfalls—short-lived connections, frequent INFO commands, and misuse of pipelines—by presenting real‑world experiments, profiling data, and source‑level analysis, then offers concrete code changes and best‑practice recommendations to reduce CPU and memory overhead.

CPUMemoryOptimization
0 likes · 15 min read
Why Short Connections, Frequent INFO Calls, and Pipelines Hurt Redis Performance (and How to Fix It)
Architects' Tech Alliance
Architects' Tech Alliance
Sep 20, 2019 · Industry Insights

Why Heterogeneous Parallel Computing Is the Future of High‑Performance Computing

The article explains how heterogeneous parallel computing—distributing tasks across CPUs, GPUs, FPGAs and other accelerators—has become essential after Moore’s law plateau, detailing its principles, hardware and software perspectives, classification of architectures, processing stages, user‑guided versus compiler‑guided methods, and its relevance to AI, cloud and industry workloads.

CPUFPGAGPU
0 likes · 15 min read
Why Heterogeneous Parallel Computing Is the Future of High‑Performance Computing
Architects' Tech Alliance
Architects' Tech Alliance
Sep 6, 2019 · Fundamentals

Understanding the Differences Between CPU and GPU Architectures

CPU and GPU serve distinct roles in computing: the CPU, as a versatile general‑purpose processor, handles complex logic and varied data types, while the GPU, built with many simple cores and long pipelines, excels at parallel processing of uniform, large‑scale data such as graphics and AI workloads.

AICPUGPU
0 likes · 10 min read
Understanding the Differences Between CPU and GPU Architectures
Architects' Tech Alliance
Architects' Tech Alliance
Sep 3, 2019 · Fundamentals

Fundamentals of CPU Architecture and Performance

This article explains the fundamentals of CPUs, covering their core functions, internal components, operation stages, key performance metrics such as clock speed, multiplier and external frequency, as well as modern technologies like Turbo Boost, multi‑core, hyper‑threading, and the evolution of CISC and RISC architectures.

CPUHyper-Threadingcomputer fundamentals
0 likes · 11 min read
Fundamentals of CPU Architecture and Performance
ITPUB
ITPUB
Aug 14, 2019 · Fundamentals

How CPUs Execute Programs: From Fetch to Cache and Multithreading Explained

This article explains the core principles of CPU operation, covering instruction fetching, decoding, execution cycles, register types, pipeline and superscalar architectures, multi‑core and hyper‑threading designs, as well as the hierarchy of caches from registers to L3, providing a comprehensive overview of modern processor fundamentals.

CPUcachesinstruction cycle
0 likes · 13 min read
How CPUs Execute Programs: From Fetch to Cache and Multithreading Explained
Programmer DD
Programmer DD
Jul 18, 2019 · Backend Development

How to Detect and Resolve Java Deadlocks and 100% CPU Issues: A Step‑by‑Step Guide

This article walks Java developers through diagnosing and fixing common problems such as deadlocks and CPU usage spikes, explaining the underlying concepts, showing practical code examples, and demonstrating how to use tools like jps, jstack, JConsole, JVisualVM, and Arthas to pinpoint and prevent performance bottlenecks.

ArthasCPUDeadlock
0 likes · 10 min read
How to Detect and Resolve Java Deadlocks and 100% CPU Issues: A Step‑by‑Step Guide
Architects' Tech Alliance
Architects' Tech Alliance
Jun 22, 2019 · Fundamentals

Illustrated Full Process of Intel Core i7 CPU Production and Architecture Overview

This article provides a comprehensive, illustrated guide to the entire manufacturing workflow of an Intel Core i7 CPU—from raw silicon extraction and purification, through photolithography, doping, and multilayer metal deposition, to testing, packaging, and future architectural outlooks including x86 limitations and the rise of RISC‑V and the RIOS lab.

CPUIntelRISC-V
0 likes · 27 min read
Illustrated Full Process of Intel Core i7 CPU Production and Architecture Overview
Efficient Ops
Efficient Ops
May 28, 2019 · Operations

Speed Up a Slow Linux PC: Check CPU, Services, Memory, and Disk I/O

This guide walks you through essential Linux performance diagnostics—examining CPU details, startup services, load averages, memory usage, and disk I/O—providing commands and practical solutions to identify bottlenecks and improve system responsiveness for your workstation.

CPUMemorySystemd
0 likes · 7 min read
Speed Up a Slow Linux PC: Check CPU, Services, Memory, and Disk I/O
58 Tech
58 Tech
May 22, 2019 · Fundamentals

Linux CPU Power Management: P‑states and C‑states in Kernel 2.6 and 4.18

This article explains how Linux kernels 2.6 and 4.18 manage CPU P‑states and C‑states, covering BIOS control, cpupower usage, idle drivers, the menu governor, MONITOR/MWAIT effects, and performance comparisons between power‑saving and performance modes on Intel Xeon E5‑2630 v4.

C-statesCPULinux
0 likes · 12 min read
Linux CPU Power Management: P‑states and C‑states in Kernel 2.6 and 4.18
Java Captain
Java Captain
May 20, 2019 · Fundamentals

Understanding Java Regex Backtracking and Its Impact on CPU Usage

The article explains how a complex Java regular‑expression used for URL validation triggers catastrophic backtracking, causing near‑100% CPU usage, and demonstrates how to analyze, reproduce, and fix the regex by reducing greedy patterns and adding missing characters.

CPUNFAbacktracking
0 likes · 11 min read
Understanding Java Regex Backtracking and Its Impact on CPU Usage
21CTO
21CTO
Apr 28, 2019 · Fundamentals

How Does a Single Java Line Execute? From CPU to JVM Explained

This article walks through the complete journey of a single Java statement—from high‑level source code, through compilation to bytecode, JVM interpretation and JIT compilation, down to CPU instruction fetching, decoding, execution, caching, memory hierarchy, threading, interrupts, and the underlying Linux process model.

CPUJVMLinux
0 likes · 34 min read
How Does a Single Java Line Execute? From CPU to JVM Explained
Architecture Digest
Architecture Digest
Apr 28, 2019 · Fundamentals

Understanding How a Single Java Statement Is Executed: From CPU Architecture to JVM Memory Model

This article explains the complete execution path of a single Java line—from the Von Neumann CPU components, instruction fetch‑decode‑execute pipeline, Java bytecode generation, JVM class loading and interpretation, memory layout and caching, to Linux process memory management, thread scheduling, synchronization mechanisms and timer implementation—providing a deep technical foundation for Java performance tuning.

CPUJVMMemory Model
0 likes · 33 min read
Understanding How a Single Java Statement Is Executed: From CPU Architecture to JVM Memory Model