This article walks through twenty essential PyTorch concepts—from basic Tensor creation and manipulation, through autograd and neural‑network construction, to data loading, GPU acceleration, model saving, and practical training tricks—providing concrete code examples and clear explanations for developers eager to build and deploy AI models.
This article explains how to implement three complex visual effects—Strange Attractor, Fibonacci Sphere, and Galaxy animations—in Flutter using only Dart code, covering the underlying differential equations, Euler integration, 3D‑to‑2D projection, rotation, perspective, performance optimizations, and solutions to common GPU tile‑artifact issues.
The article explains the design, implementation, and performance of the AMem NCCL‑Plugin, a lightweight extension to NVIDIA's NCCL that enables transparent offloading and rapid recovery of GPU memory during reinforcement‑learning training of trillion‑parameter models, detailing its architecture, APIs, benchmarks, installation steps, and integration guidelines.
TileLang is a Python‑style DSL built on TVM that separates algorithm logic from hardware scheduling, offers beginner to expert interfaces, supports multiple GPU and CPU backends, and delivers performance on par with or better than existing AI kernels, as demonstrated with GEMM, FlashAttention and other benchmarks.
An in‑depth look at Linux’s DRM GPU driver framework reveals how Direct Rendering Manager, libdrm, KMS, GEM and related components collaborate to manage GPU resources, render graphics, and support multi‑display setups, complete with illustrative code examples and practical debugging tips.
Nvidia leverages its GPUs to solve quantum computers' fragile error‑correction problem, introducing ultra‑fast NVQLink interconnect and the CUDA‑Q programming platform, creating a feedback loop that secures its dominance in both traditional and emerging quantum markets.
Microsoft’s CEO Satya Nadella admits the tech giant’s massive stock of Nvidia GPUs are idle due to insufficient electricity and lack of ready‑to‑use data‑center facilities, highlighting a broader industry shift where AI’s soaring compute demand is now constrained by power and infrastructure limits.
Microsoft’s CEO reveals that massive GPU inventories are idle because of insufficient electricity and lack of ready‑to‑use data‑center space, highlighting a broader industry challenge where power infrastructure, not chip supply, is becoming the bottleneck for AI expansion.
This tutorial explains how to leverage Linux kernel tracepoints with eBPF and bpftrace to capture real‑time GPU driver activity—including job scheduling, memory management, and command submission—across Intel, AMD, Nouveau, and NVIDIA GPUs, providing detailed examples, scripts, and analysis of the resulting data.
After NVIDIA’s abrupt exit from the Chinese market, domestic AI chip makers such as Huawei Ascend, Cambricon, Moores Thread, and Muxi are rapidly filling the gap, with increasing market share, diverse architectures, and ambitious production goals that could soon surpass foreign competitors.
Nvidia just became the first company to break the $5 trillion market‑cap threshold, a milestone that underscores its rapid growth, ambitious AI‑factory vision, 6G edge‑AI plans, autonomous‑driving initiatives, digital‑twin manufacturing, and the strategic importance of its CUDA ecosystem.
This article explains the concept of computing power, its measurement units, classifications into general and specialized types, the role of CPUs, GPUs, FPGA and ASIC chips, and how it underpins AI model training, blockchain mining, and scientific research.
Nvidia announced native Python support for its CUDA toolkit, detailing new Python‑centric APIs, projects like CuTile and Cutlass, and a layered strategy that democratizes GPU programming for AI developers while preserving performance and expanding the ecosystem.
The article explains how bpftime extends eBPF to NVIDIA and AMD GPUs, exposing fine‑grained execution details that traditional CPU‑side tools miss, and demonstrates a unified, programmable observability stack that overcomes the limitations of existing GPU profilers in both synchronous and asynchronous workloads.
This guide walks you through preparing your Ubuntu 22.04 system, disabling the Nouveau driver, removing old NVIDIA packages, and installing the latest NVIDIA driver using either the graphical Software & Updates tool or command‑line methods, followed by verification and troubleshooting tips.
After installing drivers on an NVIDIA Tesla A100, the GPU reports a constant 25% utilization despite no workload, which can be resolved by enabling persistence mode using a simple nvidia‑smi command to keep the driver loaded and improve performance stability.
This article explains the fundamentals of high‑performance computing (HPC), covering serial and parallel processing, the roles of CPUs and GPUs, system architectures, FLOPS metrics, current supercomputer capabilities, and the scale needed to reach the next exa‑FLOPS era.
This article explains how enterprise architects can integrate ONNX‑based machine‑learning inference directly into Java applications, covering tokenizer integration, GPU acceleration, deployment patterns, and lifecycle management to achieve secure, scalable, and observable AI services without relying on Python runtimes.
The article uses a whimsical journey to illustrate how token data is dispatched across GPU clusters—detailing functions like get_dispatch_layout, notify_dispatch, and combine_token, showing RDMA and NVLink pathways, performance experiments, and the final verification of token integrity.
This guide explains why Java struggles with high‑performance or data‑intensive workloads, introduces GPU acceleration with CUDA, compares integration options such as JCuda, JNI, and JNA, walks through a practical encryption use case with performance benchmarks, and provides production‑grade best practices for memory, threading, testing, security, and deployment.
An in‑depth analysis reveals that Oracle’s AI‑focused cloud business, built on expensive Nvidia GPU rentals for OpenAI and other AI developers, generates massive revenue but suffers from alarmingly low profit margins, creating a systemic risk that could ripple through the entire AI infrastructure ecosystem.
Microsoft, after buying massive GPU inventories from Nvidia and AMD, is accelerating its move to custom AI accelerators like Maia to improve cost‑performance in its data centers, even though its first‑generation chips still lag behind industry leaders.
Amid US export restrictions, China’s five‑year‑old GPU pioneer Moore Thread is racing to fill the high‑end GPU gap, detailing the technology’s role in AI, its ecosystem strategy, and the significance of its fast‑track IPO for the domestic semiconductor and AI compute landscape.
The article dissects Jensen Huang’s BG2 interview to explain Nvidia’s shift from a pure GPU supplier to an AI‑Factory architect, detailing the double‑exponential AI demand growth, token‑based economics, technical and ecosystem moats, sovereign AI initiatives, open‑link strategies, and the long‑term vision of physical AI.
This article compares Ray Serve and Celery, explaining their design philosophies, scaling models, GPU‑aware scheduling, operational trade‑offs, and real‑world case studies to help engineers choose the right tool for high‑throughput online inference or large‑scale batch processing.
This article examines how to achieve low‑latency network packet processing on NVIDIA GPUs by comparing CPU and GPU implementations, exploring memory optimizations, batch strategies, stream concurrency, persistent kernels, and CUDA graphs, and presenting detailed performance measurements for each technique.
This guide walks through configuring Windows 11 with WSL2 and Ubuntu 22.04 for GPU‑accelerated CUDA development, installing NVIDIA drivers and CUDA libraries, setting up SSH and firewall rules, running a CUDA stress‑test program, and using Nsight Systems, Nsight Compute, and NVIDIA DCGM for performance profiling and monitoring.
This guide walks you through configuring a high‑performance AI inference server on Oracle Linux, covering hardware specs, NVIDIA driver and CUDA installation, Conda environment setup, Xinference deployment, service startup, and example model loading commands, all with clear code snippets and images.
This guide walks through checking the system environment, installing the NVIDIA Docker plugin, configuring Docker to use the NVIDIA runtime, verifying GPU access, deploying the NVIDIA device plugin in a Kubernetes cluster, creating a GPU‑enabled pod, and testing GPU‑accelerated video processing with FFmpeg.
This article explains the types of AI compute chips, their market share and key performance metrics, details Nvidia's GPU architecture, and surveys the emerging Chinese AI chip manufacturers and their flagship products, providing a comprehensive overview of the AI hardware landscape.
This guide walks through deploying a local LLM on Kubernetes using Ollama for model serving and Open-WebUI for a web interface, covering namespace creation, storage setup, GPU support, service exposure, validation, and model download to ensure privacy, low latency, and high availability.
This article examines NVIDIA's Kepler GPU architecture, highlighting its 28 nm process, increased transistor count, expanded CUDA core count, PCIe 3.0 support, enhanced memory hierarchy, new compute units, scheduling improvements like Hyper‑Q, and performance metrics of the Tesla K20X, illustrating the substantial gains over previous generations.
This article walks through GPU performance analysis, starting with CUDA architecture fundamentals, demonstrating matrix multiplication optimization, explaining PTX assembly, and introducing the Neutrino framework for programmable GPU probes that enable fine‑grained, custom instrumentation and detailed timing measurements of kernel execution.
The article explains how to choose suitable large AI models for product use by focusing on three key aspects—model inference, post‑training optimization techniques such as quantization, pruning and distillation, and the role of GPUs, including their kernels, software stack, and computing platforms.
A Reuters report reveals that Nvidia’s China‑specific B30A GPU may cost up to $24,000, double the price of the current H20 chip, while Chinese AI developers continue to favor Nvidia despite government pushes for domestic alternatives and shifting US export policies.
The article traces the evolution of AI hardware over the past ten years, outlining three key phases—from early chip limitations that sidelined neural networks, through CPU advances that still fell short, to the rise of GPUs and specialized AI chips that finally unlocked rapid AI deployment, while also highlighting the parallel impact of algorithmic breakthroughs and massive data growth.
This guide walks through creating a Kubernetes Operator using Kubebuilder to manage a GPU spot‑pool on Tencent Cloud, covering CRD design, controller logic, code generation, and deployment steps, enabling automated scaling of GPU resources for AI workloads while illustrating core Cloud‑Native concepts.
This article explains why traditional load‑balancing methods fall short for large language model services and introduces Higress AI Gateway's three specialized algorithms—global minimum‑request, prefix‑matching, and GPU‑aware load balancing—detailing their design, Redis‑based implementation, deployment steps, and performance gains.
This article presents a comprehensive, step‑by‑step analysis of a high‑throughput, asynchronous OCR pipeline built with Spring Boot and Tesseract, covering system architecture, thread‑pool tuning, custom invoice‑specific model training, multi‑engine fusion, structured data extraction, performance optimizations, GPU acceleration, Kubernetes deployment, monitoring, security compliance, chaos testing, and future evolution plans.
This article traces the evolution of NVIDIA GPU architectures—from the early Tesla series through Fermi, Kepler, Maxwell, Pascal, Volta, Turing, Ampere, Hopper, and up to the upcoming Blackwell—explaining their hardware innovations, CUDA programming model, and how each generation enabled breakthroughs in high‑performance computing, deep learning, and AI applications.
This article breaks down the hardware bottlenecks of large‑scale LLM training, explains the Roofline performance model, arithmetic intensity, and how computation and communication costs interact on GPUs and TPUs, offering concrete formulas and examples for efficient scaling.
Burn, a native Rust deep learning framework by Tracel AI, combines extreme flexibility, high computational efficiency, and cross‑platform portability through a modular backend abstraction, type‑safe tensor operations, asynchronous execution, and extensive tooling, offering performance‑competitive alternatives to Python‑based frameworks for both training and inference.
AMD's Advancing AI 2025 event unveils the next‑generation Instinct MI350 GPU, the ROCm 7 AI software stack, and the upcoming Helios rack built on MI400 GPUs, Zen 6 EPYC “Venice” CPUs and Pensando NICs, outlining a bold open‑standard AI infrastructure roadmap.
This article surveys a wide range of Python performance‑enhancing tools—from NumPy and Cython to JIT compilers like PyPy and GPU libraries such as PyCUDA—explaining how each can simplify code, accelerate execution, and help developers choose the right approach for single‑ or multi‑processor environments.
Huawei is developing a new AI‑focused GPU‑style chip that mirrors Nvidia and AMD architectures, aiming to ease Chinese developers’ shift from Nvidia hardware, but still faces software compatibility hurdles due to reliance on CUDA and ongoing U.S. export restrictions.
This article provides a comprehensive analysis of the GPU industry, covering its definition, parallel‑computing advantages, core functions, API evolution, micro‑architecture, market size forecasts, competitive landscape, and the impact of geopolitical restrictions on future development.
Huawei is developing a new AI chip that functions more like a general‑purpose GPU, aiming to match Nvidia and AMD architectures and simplify the transition for Chinese AI developers, while still facing challenges such as adapting CUDA‑based software and overcoming export restrictions.
The article explains that GPUs, with thousands of simple cores and high‑bandwidth memory, excel at the massive parallel matrix computations required by large‑scale language model training, while CPUs handle control and scheduling, making the two processors complementary for AI workloads.
This article explains how modern GPUs evolved from graphics rendering to general‑purpose computing, details the CPU‑GPU heterogenous architecture, walks through a CUDA demo that adds two billion‑element arrays, compares CPU and GPU performance, and describes the compilation, loading, and execution pipeline of CUDA kernels.
This article explores how GPUs evolved from graphics accelerators to general‑purpose processors for AI, detailing the CPU‑GPU heterogeneous architecture, the CUDA programming workflow, compilation into fat binaries, kernel launch mechanics, hardware components, and the differences between SIMD and SIMT models, with performance comparisons and code examples.
This guide explains why Java architects should understand CUDA, describes the GPU programming model, compares CPU and GPU designs, and details three practical ways—JNI, JCuda, and TornadoVM—to integrate CUDA acceleration into Java applications, with tips for using A100 GPUs effectively.
This comprehensive guide covers 100 essential GPU fundamentals, from basic definitions and architecture to core technologies, performance optimization, emerging trends, and industry developments, providing a complete technical foundation for graphics, AI, and high‑performance computing applications.
This article examines how to centrally manage GPU resources across heterogeneous Kubernetes clusters using namespace‑based RBAC isolation, virtual control‑plane solutions like vcluster, and multi‑cluster tools such as Karmada, comparing their architectures, use cases, advantages, and limitations to guide enterprise‑level deployment decisions.
This comprehensive guide covers GPU definitions, evolution, core components, architectural designs, performance metrics, programming models, deep‑learning applications, comparisons with other processors, practical use cases, optimization techniques, and future trends, providing a solid foundation for anyone interested in modern graphics and compute acceleration.
This tutorial walks you through using a one‑click script to create a GPU‑enabled Kind Kubernetes cluster, evenly distribute GPU resources across nodes with nvkind, install necessary drivers and toolkits, deploy a vLLM‑served large language model, and verify its operation, all on a local or cloud environment.
In March 2024 Nvidia unveiled the Blackwell GPU family and the GB200 NVL72 architecture, featuring 3‑4 nm processes, redesigned CUDA cores, next‑gen ray‑tracing, upgraded DLSS, massive FP16/FP8 compute gains, 8 TB/s memory bandwidth, and NVLink Gen5, while also presenting complex power, cooling, and packaging challenges for large‑scale AI deployments.
The article explains why standard GEMM libraries may fall short for special matrix shapes, introduces NVIDIA’s open‑source CUTLASS library, details its hierarchical tiling architecture, and walks through a complete device‑API example that customizes tile sizes and data layouts to achieve near‑hand‑written kernel performance on modern GPUs.
This article compares NVIDIA’s China‑specific B30 and high‑end H20 GPUs, detailing their CPU/CPU architecture updates, memory technologies, architectural differences, performance metrics, power and cooling characteristics, and price positioning, to help enterprises and developers choose the most suitable accelerator for AI and deep‑learning tasks.
The Chinese AI server market is booming, with GPU servers still dominant while non‑GPU accelerators surge, IDC forecasts a compound annual growth above 20% through 2028, and leading vendors such as Inspur, H3C, and emerging Ascend‑based manufacturers reshaping the competitive landscape.
Coupang’s AI platform replaces costly data‑copy steps with a distributed cache that automatically pulls data from a central lake, boosts GPU utilization across regions, cuts storage and operational expenses, and speeds up model training by up to 40% while simplifying deployment via Kubernetes.
NVIDIA announced at GTC 2025 that CUDA will now natively support Python, allowing developers to write GPU‑accelerated code directly in Python without C/C++ knowledge, introducing new APIs, libraries, JIT compilation, performance tools, and a tile‑based programming model that aligns with Python’s array‑centric workflow.
This article traces the history of graphics GPUs from their 1980s origins to modern AI and high‑performance computing roles, examines China's emerging GPU market and its challenges, and reviews the key graphics and compute standards shaping the industry today.
This article explains the concepts of AI Pods and GPU clusters, compares vertical (scale‑up) and horizontal (scale‑out) expansion, describes XPU types, discusses internal and inter‑pod communication, and evaluates the benefits and drawbacks of each scaling approach along with relevant networking technologies.
NVLink Fusion, unveiled at Computex 2025, extends NVIDIA’s NVLink technology to enable high‑bandwidth, low‑latency connections between CPUs and GPUs or third‑party accelerators, offering up to 900 GB/s bandwidth, flexible heterogeneous configurations, ecosystem expansion, performance gains for AI training and inference, and potential cost reductions.
This article examines the impact of U.S. export restrictions on Nvidia’s China‑specific GPU lineup, detailing the specifications and architectural changes of the H20, B20, and B40 chips, while also discussing domestic alternatives and the broader implications for AI compute in China.
This article provides a comprehensive analysis of GPU core parameters—including compute units, memory systems, floating‑point performance, power consumption, and manufacturing process—while comparing leading international and domestic GPU products to help readers choose the right accelerator for AI, HPC, or graphics workloads.
A US Senate bill introduced by Senator Tom Cotton requires Nvidia, AMD, Intel and other high‑end GPU and AI processor makers to embed geolocation tracking, imposing six‑month compliance deadlines, new reporting obligations, and potentially billions of dollars in added R&D and export‑control costs.
This roundup highlights Tencent's GPU capacity for future models, Alibaba's fully disclosed Qwen3 technical report, Anaconda's unified AI platform, Parasoft's AI‑enhanced SOAtest, and Google Cloud's GA of the Apigee API Management Operator, offering a snapshot of current AI advancements.
This article analyzes NVIDIA's evolving AI supercomputer architectures—detailing the H100‑based 256‑GPU SuperPod, the GH200‑based 256‑GPU SuperPod with integrated Grace CPU, and the GB200‑based 576‑GPU SuperPod—examining their NVLink and InfiniBand topologies, bandwidth limits, and scalability challenges.
NVIDIA announced native Python support in its CUDA toolkit, enabling developers to write GPU‑accelerated code directly in Python, detailing the new programming model, JIT‑based architecture, performance benefits, and the broader impact on AI development and the developer ecosystem.
The article describes how a large‑scale dispatch system was re‑engineered with NVIDIA TritonServer to unify GPU‑accelerated operations‑research kernels and deep‑learning models, detailing a three‑stage architecture (in‑process, cross‑process, cross‑node), the performance, stability and memory challenges addressed, and future plans for heterogeneous GPU scaling.
This guide walks you through cross‑platform environment variable configuration, Docker containerization, GPU resource strategies, concurrency tuning, and security hardening for Ollama, providing practical code snippets and best‑practice tables to unleash its full potential in development and production.
This guide explains how to prepare, deploy, and verify the Qwen3‑8B large language model on an Alibaba Cloud Container Service for Kubernetes (ACK) cluster using ACS GPU resources, covering prerequisites, model download, storage setup, Kubernetes manifests, and testing the inference service.
This article provides a comprehensive analysis of modern server architecture, covering the evolution from CISC to RISC, the rise of heterogeneous computing with GPUs and accelerators, diverse form factors, core component technologies, reliability mechanisms, performance benchmarking, certification standards, and emerging trends such as liquid cooling and AI‑native designs.
This article objectively compares AMD and NVIDIA graphics cards for Linux users, covering out‑of‑the‑box driver support, Wayland compatibility, gaming performance, machine‑learning capabilities, and cost‑effectiveness to help readers choose the best GPU for their needs.
This article presents a detailed comparison of major NVIDIA GPUs—including RTX 4090, RTX 4090 D, RTX 3090, A10, A40, A100, and H100—covering memory size, bandwidth, Tensor BF16/FP16/FP32 throughput, FP16/FP32 performance, power draw and release dates, and explains how these specs affect AI workload efficiency.
This article analyzes NVIDIA's A100, H100, A800, H800, and H20 GPUs, compares their architectures, performance, and pricing, and provides a step‑by‑step guide for building a private AI compute center tailored to training, inference, and high‑performance computing workloads.
This guide explains how Alibaba Cloud's ACK One registered cluster provides multi‑region serverless GPU compute scheduling, addressing AI workload elasticity by using region‑specific labels, ResourcePolicy, and the ack‑co‑scheduler to automatically balance resources across regions.
This article analyzes the Xinchuang hardware ecosystem and server industry from 2024 to 2026, covering supply‑chain structure, shipment growth, market share, competitive tiers, downstream application demands, and the technical and ecological challenges that hinder full domestic substitution.
At the recent GTC conference Nvidia unveiled its roadmap of AI‑focused GPUs—Ampere, Hopper, Blackwell, Rubin and the upcoming Feynman—each named after a pioneering scientist, and this article explores the historical contributions of André‑Marie Ampère, Grace Hopper, David Blackwell, Vera Rubin and Richard Feynman, linking their legacies to the architectures’ innovations.
As AI models grow to trillion‑parameter scales, training them demands massive GPU clusters whose performance is increasingly limited by network bandwidth; this article examines why traditional PCIe interconnects become bottlenecks and how NVIDIA's NVLink and NVSwitch technologies dramatically improve multi‑GPU communication and overall system efficiency.
This article analyzes the AI compute chip ecosystem, covering GPU, FPGA, and ASIC categories, market share projections, key performance metrics such as TOPS, power and area, and provides a detailed overview of leading global vendors and emerging Chinese companies with their technical specifications and competitive positioning.
This article explains how to dramatically speed up PyTorch model training using code optimizations, mixed‑precision, torch.compile, distributed data parallelism, and DeepSpeed, presenting benchmark results that show up to 11.5× acceleration on multiple GPUs while maintaining high accuracy.
Training today's massive AI foundation models demands extensive GPU resources and sophisticated multi‑GPU communication, making technologies like NVLink and NVSwitch crucial for efficient distributed training, while data‑parallel and model‑parallel strategies together optimize performance across large‑scale hardware clusters.
This article presents a comprehensive benchmark of DeepGEMM, Cutlass, and Triton on NVIDIA H20 and H800 GPUs, analyzing TFLOPS, bandwidth, latency, and speedup across various matrix sizes, and concludes which library is optimal for different workload scenarios.
This article explains scientific notation, the IEEE‑754 floating‑point standard, the structure of FP32 and FP64 numbers, and how computational power is measured using FLOPS, illustrating CPU and GPU FP32 performance calculations and why FP32 is the common benchmark for AI workloads.
The article traces NVIDIA’s GPU architecture evolution from the Volta era’s pioneering Tensor Cores through Turing, Ampere, Hopper, and the latest Blackwell and Rubin designs, highlighting key innovations such as mixed‑precision support, sparsity, NVLink, and their impact on deep‑learning performance.
This article provides a comprehensive analysis of the GPU industry, covering product classifications, key characteristics, market size evolution, competitive dynamics among major players such as NVIDIA, AMD, and Huawei, policy influences, and future growth projections driven by AI and high‑performance computing demands.
This article explains the rise of AI‑specific processors, defines AI chips, compares their architectures, and examines the distinct requirements of training versus inference chips while outlining the main technology routes (GPU, FPGA, ASIC) and future outlook.
This article explains the cuda‑python ecosystem—including its core packages, installation via pip or conda, the experimental cuda.core API, a full Python‑to‑CUDA workflow with NVRTC compilation, performance comparison to C++, the covered APIs, and an overview of NVIDIA's new cuTicle programming model.
The article reviews Nvidia GTC 2025’s session on writing CUDA kernels with Python, compares tools such as Numba, CuPy, PyTorch extensions and cuda‑python, demonstrates a segmented reduction example with C++ and Python code, explains the underlying CUDA concepts, and shows how to install and use cuda‑python to simplify kernel development.
The article explains GPU fundamentals—from the end of Dennard scaling and why GPUs excel in parallel throughput, through CUDA programming basics like the SAXPY kernel and SIMT versus SIMD execution, to the evolution of the SIMT stack, modern scheduling, and a three‑step core architecture design.
The article explains the theoretical and practical relationships between GPU clock frequencies, power consumption, and FLOPS, describes key hardware metrics such as SM, memory, and video clocks, shows how to query and set these values with nvidia‑smi, and presents experiments on a Tesla P4 that reveal the non‑linear trade‑offs between performance, power, and temperature.
This article details JD Retail's AI engine that seamlessly supports both GPU and domestic NPU hardware, describing its heterogeneous cluster architecture, unified training and inference APIs, performance optimizations, extensive model coverage, and multiple production use cases across e‑commerce, logistics, and intelligent assistance.
At HPCA 2025, two standout papers—UniNDP, a unified compilation and simulation tool for near‑DRAM processing architectures, and WarpDrive, a GPU‑based fully homomorphic encryption accelerator leveraging Tensor and CUDA cores—demonstrate significant performance gains for AI workloads and privacy‑preserving computation.
This article analyzes Nvidia’s evolution from a graphics pioneer to an AI hardware leader and examines Huawei’s Ascend AI processor roadmap, detailing technical specifications, ecosystem strategies, recent product releases, and the potential impact on related technology stocks.
This article compiles a market overview of 52 DeepSeek integrated machines, detailing GPU chips, price ranges from tens of thousands to millions, major Chinese cloud vendors, and diverse application scenarios such as intelligent customer service, data processing, and smart governance.
This guide walks through checking the system environment, installing the NVIDIA Docker plugin, configuring Docker to use the NVIDIA runtime, verifying GPU access with Docker, deploying the NVIDIA device plugin on a Kubernetes cluster, and running GPU‑accelerated workloads in pods.
The article summarizes Zhihu's machine‑learning platform lead Wang Xin's presentation on the ZhiLight large‑model inference framework, covering model execution mechanisms, GPU workload analysis, pipeline and tensor parallelism, GPU architecture evolution, open‑source engine comparisons, ZhiLight's compute‑communication overlap and quantization optimizations, benchmark results, supported models, and future directions.
This tutorial explains how to set up Ollama for CPU or GPU environments, run the DeepSeek R1:7b large language model, and use the open‑source Dify platform to create and deploy a custom AI application, providing step‑by‑step commands and configuration details.
